Gated Clock and Revised Keeper (GCRK) Domino Logic Design in 16 nm CMOS Technology

ABSTRACT

This paper proposed a domino logic namely “Gated Clock and Revised Keeper (GCRK)” domino logic 16 nm CMOS technology. The proposed domino logic has a revised keeper circuitry to reduce the power consumption in the circuit. A multiplexer is added in the GCRK design for gating the clock signal during sleep mode while maintaining the state of the domino logic. Total power consumption, delay and power-delay-product (PDP) of 16-bit OR gate GCRK domino logic and existing domino logic designs are calculated and compared. The existing domino logic techniques considered in this paper are – Leakage tolerant multiphase keeper domino logic (LTMK), high-speed domino logic (HSD), clock delayed sleep mode domino logic (CDSMD), grounded pmos keeper domino logic (GPKD) and foot driven stack transistor domino logic (FDSTDL). The proposed design shows significant improvement in PDP with respect to the existing designs. The PDP of proposed design (LTMK) is improved to 99.98%, 88.75%, 11.54% and 37.11% as compared to LTMK, HSD, GPDK and FDSTDL designs, respectively. Noise analysis and Monte Carlo simulation show that the proposed design is immune to noise and reliable under different parametric variations.

KEYWORDS:

• Clock gating
• CMOS
• Domino
• Dynamic
• Keeper
• Static power

Disclosure statement

No potential conflict of interest was reported by the authors.

Additional information

Notes on contributors

Smita Singhal

Smita Singhal was born in Mathura, India in 1981. She received the BTech degree from UP Technical University, Lucknow, India in 2004 and MTech degree from Banasthali Vidyapith, Rajasthan, India in 2007. She joined Patni Computer Systems, India in 2007 where she worked as a software engineer. To pursue her career in teaching, she joined Amity University, Noida, India in 2009 as an assistant professor. She is PhD in engineering from Amity University, Noida, India. Her main areas of interest are low power CMOS design and digital circuits.

Anu Mehra

Anu Mehra received her Masters in Engineering from KU Leuven, Belgium in the year 1998. She received PhD in “High Energy physics” from Jamia Millia Islamia, Delhi, India in 2004. After the completion of PhD, she went for a post doc to IMEC, Belgium. She also did a complementary Masters in Engineering there. She joined Amity University, Noida, India in the year 2004. Currently, she is working as professor in Amity School of Engineering and Technology in the Department of Electronics and Communications Engineering. Email: [email protected]