Design and Optimization of Reversible Logic Based Magnitude Comparator Using Gate Diffusion Input Technique

Abstract

The power optimization is one of the biggest challenging issues for designing of VLSI circuits within the advanced technology. The reversible logic is one among the best approaches for low power application. This logic has wide applications in the communication, nanotechnology, digital signal processing, computer graphics, optical computing, etc. In this paper, some proposed reversible magnitude comparator has been designed using the prevailing reversible gates and implemented using gate diffusion input (GDI) technique. The design methodologies are also proposed for the designing of N-bit comparator. The main objective of this paper is to design and implementation of reversible magnitude comparator using some proposed methods and compares them with the existing circuits in terms of constant input, garbage output, number of reversible gates, and quantum cost. The transistor implementations of the proposed comparators are done by the combination of CMOS and GDI technique in EDA Tanner tools. After the design and analysis of proposed comparators it has been found that the proposed-2 logic based 4-bit comparator has lowest quantum cost which is equal to 38 and the proposed-3 logic based 4-bit comparator has lowest constant input and garbage output which is equal to 8 and 13.

KEYWORDS:

• Constant input
• Garbage output
• Gate diffusion input
• Magnitude comparator
• Reversible gate
• Quantum cost
• Transistor count

Additional information

Notes on contributors

Dwip Narayan Mukherjee

Dwip Narayan Mukherjee was awarded MTech in ECE from Burdwan University, Burdwan, India. He is currently working as assistant professor in Electronics and Communication Engineering Department of Bankura Unnayani Institute of Engineering, West Bengal, India. He has 14 years of academic experience. He has published more than 10 research articles in peer-reviewed international journals, national and international conferences. His research interest is in the area of VLSI low power design, image processing, and signal processing.

Saradindu Panda

Saradindu Panda has been serving as HOD of Electronics and Communication Engineering Department of Narula Institute of Technology, Agarpara, Kolkata for nine years. He received PhD in ECE from NIT, Durgapur in 2014. He received his BE degree in ECE from UIT, Burdwan University in 2004 and MTech degree in VLSI and microelectronics technology from Jadavpur University in 2007. He is also a National Scholarship winner at his school level. He is a professional member of IEEE, professional member of IET, Institutional member of IETE. His research interests include Low power and High speed VLSI circuit design, noise modelling and analysis of advanced semiconductor devices like DGMOSFET, SGMOSFET, MESFET, HEMT, etc., design of SOCs, VLSI signal processing, advanced digital system design and embedded system design. He has published one Book on Microelectronics and Optoelectronic Devices and more than 60 research articles in peer-reviewed international journals, national and international conferences. Email: [email protected]

Bansibadan Maji

Bansibadan Maji is now a senior professor of ECE Department in NIT, Durgapur, West Bengal, India. His main research area is on microwaves, antenna, VLSI design, and low power device and circuits. He has more than 80 publications in different International and national journals and conference proceedings to his credit. Email: [email protected]