Design of an Efficient Multilayer Hybrid Reversible Spintronic Ripple Carry Adder Using Quantum Cellular Automata Technique

Abstract

Quantum-Dot-Cellular-Automata (QCA) using Spintronic electrons is a promising alternative to the traditional CMOS technology in this modern era to design any nano-sized electronic structure. The majority of the current digital components are being designed using QCA-cell-interaction. In some cases, reversible logic with the Spintronic-QCA-technique is also being explored to design various digital components. Because of this, the various aspects for the design of a novel hybrid QCA-based Spintronic advance reversible adder and its efficiency measures are presented in this research work by investigating area-occupation, temperature-tolerance, delay, power dissipation, and output strength. The results obtained in this work establish that the proposed design is more efficient in all respect compared to existing designs reported in recent literature. In this paper, 18nm quantum cells are used to design the proposed structure and when the power dissipation based on the total occupied cell area is calculated (100W/cm²), it is found that there is an assurance to get an adder structure with the less occupied area, less power dissipation and higher speed compared to previously published referred design. The temperature-tolerance and output-strength increment with layer separation gap reduction in multilayer platforms are also some additional advancements of the proposed structure, which are also clearly reflected. In this paper, QCA-based “Ripple-Carry-Adder (RCA)” is designed using Spintronic reversible logic in multilayer mode with different composite elements along with a “3-input-majority-voter-gate (MG)” to make the design more compact. QCADesigner 4.0 tool is used as widespread simulation trains to validate the design outcomes and measure different parameters individually.

Keywords:

• 3D hybrid
• Full adder
• Quantum cell automata
• Reversible
• Ripple carry adder
• Spintronic-electron
• Temperature tolerance

Disclosure statement

No potential conflict of interest was reported by the author(s).

Additional information

Notes on contributors

Rupsa Roy

Rupsa Roy is working as a PhD scholar in Sikkim Manipal Institute of Technology under Sikkim Manipal University, Sikkim. She has applied her MTech degree in VLSI and embedded system from Kalinga Institute of Industrial Technology (KIIT, Bhubaneswar) in the year 2018 and BTech degree in applied electronics and instrumentation from Future Institute of Engineering and Management under Maulana Abul Kalam Azad University of Technology, West Bengal in the year 2015. She has published paper in three international journals and three published conference papers in IEEE and Springer. Email: [email protected]

Swarup Sarkar

Swarup Sarkar is a well-known professor in the field of VLSI design and micro-chip design. He is working as a professor in Sikkim Manipal University, Sikkim, India. Dr Swarup Sarkar has received his PhD in VLSI & micro chip design from NIT, Durgapur, India. Dr Sarkar is the author of 48 papers in SCI/SCIE international journals, 3 books. guided several PG students and currently guiding n number of PhD scholars. He also serves as the reviewer of different journals in Springer, IEEE Transactions. He was also an invited chair speaker of international Gene convention. He is currently the PI of a project on micro chip design (sanctioned amount of 10 Lacs). He is a Member of the Institute of Electrical and Electronics Engineers (IEEE).

Sourav Dhar

Sourav Dhar was born in Raiganj, West Bengal, India, in 1980. He received BE degree from Bangalore Institute of Technology, VTU in 2002. He received MTech degree in digital electronics and advanced communication from Sikkim Manipal University in 2005 and PhD in 2013. Since 2003, he has been associated with the Sikkim Manipal Institute of Technology, India, where he is currently working as professor and head of ECE Department, SMIT. His current research interests include IoT, WSN, remote sensing, lowpower devices and microwave filter design. He is currently the PI of a project on Microwave filter design (Sanctioned amount Rs.10Lacs). He is a Senior Member of the Institute of Electrical and Electronics Engineers (IEEE), (IEEE-GRSS society) and Member of Institution of Engineers (India)(IEI). He has published more than 30 papers in SCI/Scopus indexed international journal and conferences and guided several PG students and currently guiding three PhD scholars. He also serves as the reviewer of Wireless Personal Communication, Springer, IEEE Transactions on Vehicular Technology and several other journals and conferences. Emails: [email protected], [email protected]