Bio-Inspired Methods for Defect-Tolerant Function-Mapping in Nano-Crossbar Arrays

Abstract

Nanoscale chips inherently suffer from higher defect densities than traditional lithography-based VLSI designs. So defect tolerant designs are required at this scale. Mapping different functions in a very large nanoscale crossbar containing defective cross-points is a hard searching problem. In this work, we studied traditional sorting-based methods followed by two other proposed approaches based on Genetic Algorithm (GA) and Particle Swarm Optimization (PSO) to find a proper assignment of different functions in the nanoscale crossbar circuit having defective cross-points. The objective of the proposed algorithm is to map a very large number of functions within the very large size defective-crossbar if there exists any solution. The number of generations required to get a solution may vary depending on the position of defect points and on-inputs of the functions inspite of having the same defect percentage. Our proposed methods based on GA and PSO work more efficiently with the increase of number of functions, crossbar area and defect percentage in comparison with the traditional sorting-based methods. Experimental results show that our meta-heuristic-based approaches outperform the earlier sorting-based approaches in terms of mapping success percentage.

Keywords:

• Nanoscale
• Lithography
• Crossbar
• Nanowires
• Genetic algorithm
• Particle swarm optimization

Disclosure statement

No potential conflict of interest was reported by the author(s).

Additional information

Notes on contributors

Malay Kule

Malay Kule has been on the faculty of the Indian Institute of Engineering Science and Technology (IIEST), Shibpur, India since 2013, where currently, he is an assistant professor (Grade II) of computer science and technology. Previously he served as an assistant professor in the Department of Computer Science and Engineering of St. Thomas' College of Engineering and Technology, Kolkata, India from 2006 to 2013. He received the B Sc degree in physics honors, the BTech and MTech degrees in computer science and engineering, all from the University of Calcutta, India. He received PhD degree in Engineering from the Indian Institute of Engineering Science and Technology, Shibpur, India. His research interests include defect tolerance and testing of nanoscale circuits, cryptology, and hardware security. He has published more than 35 research papers.

Habibur Rahaman

Habibur Rahaman received the BTech and MS degrees in computer science and engineering from the Maulana Abul Kalam Azad University of Technology, Kolkata, India and Indian Institute of Technology Kharagpur, India, respectively. Currently, he is pursuing PhD degree in the Department of Electrical and Computer Engineering (ECE) at the University of Florida, USA. His research interests include VLSI design and testing, machine intelligence and hardware security. He has published 8 research papers in journals and conference proceedings. Email: [email protected]

Hafizur Rahaman

Hafizur Rahaman (SM’10) received his PhD degree in computer science and engineering from the Jadavpur University, Calcutta, India in 2003. Currently, he is professor of Indian Institute of Engineering Science and Technology (IIEST), Shibpur, India. He visited as post doctoral research fellow under EPSARC grant at the Department of Computer Science, Bristol University, UK during 2006–2007. During 2008–2009, He received a Royal Society International Fellowship award to carry out one-year advanced research in the Design and Verification Division of Computer Science Department, University of Bristol, United Kingdom. Later, he received DST-DAAD research fellowship under Indo- German (DST-DAAD) Bilateral Cooperation in 2013. His research interests include design and testing of integrated circuits and nano-biochips, emerging nanotechnologies including reversible computing. He has published more than 400 research articles in archival journals and refereed conference proceedings. He leads the VLSI design and test group at IIEST, Shibpur, India. Dr Rahaman is a Member of the VLSI Society of India (VSI), the IEEE, the IEEE Computer Society, and ACM Sigda. He is reviewer of IEEE TCAD, IEEE TVLSI, IEEE TC, and ACM TODAEs. He served on the conference committees of VLSI Design, VDAT, ATS, ISED, ISPD etc. Email: [email protected]

Bhargab B. Bhattacharya

Bhargab B Bhattacharya has been on the faculty of the National Institute of Technology Rourkela, India since 2022, where currently, he is a visiting professor of computer science and engineering. Prior to that he served as professor in the Computer and Communication Sciences Division at Indian Statistical Institute, Kolkata, India during 1982 to 2018. He received the BSc degree in physics, the BTech and MTech degrees in radiophysics and electronics, and the PhD degree in computer science, all from the University of Calcutta, India. He held visiting professorship at the University of Nebraska-Lincoln, and at Duke University, USA, at the University of Potsdam, Germany, at the Kyushu Institute of Technology, Iizuka, Japan, at Tsinghua University, Beijing, China, and at IIT Kharagpur, and IIT Guwahati, India. His research interest includes design and testing of integrated circuits, microfluidic chips,digital geometry, and image processing architecture. He has published more than 450 technical articles, and he holds 10 United States Patents. He is a Fellow of the Indian National Academy of Engineering, a Fellow of the National Academy of Sciences (India), and a Fellow of the IEEE. Email: [email protected]