Capacity planning for integrated circuit final test plants

Abstract

This paper proposes a capacity planning system (CPS) to determine the capacity of machines and kits in integrated circuit final test plants. CPS applies the concept of workload levelling and infinite capacity planning on dual resources. CPS consists of four modules: Work-in-Process (WIP)-Pulling Module (WPM), Lot Release Module (LRM), Workload Accumulation Module (WAM) and Workload Balance Module (WBM). The WPM pulls WIP from the end of the process route to meet the master production schedule (MPS). If WIP cannot meet the MPS requirement, LRM is executed. WAM simultaneously accumulates the workload to conduct an IC final test machine and kit on a daily basis. WBM levels the loading of machines and kits by adjusting the lot starting time with the use of these resources. CPS is developed in Microsoft Visual Basic, and industrial data are used to test its performance. The experimental design includes four factors: workload balance heuristics, MPS variation, MPS variation frequency and product mix. The simulation results are analysed by using descriptive statistics and ANOVA. The results show that CPS is effective and efficient in balancing the workload of resources, including machines and kits.

Keywords:

• integrated circuit
• final test
• capacity planning
• semiconductor manufacturing

Additional information

Funding

The authors gratefully acknowledge the National Science Council, Taiwan, R.O.C., for support under contract [NSC 100-2622-E-007-022-CC2].