Figures & data
Figure 1. Schematic of (a) the stacked TFT with IGZO/Al2O3 using in situ PEALD (1S, 3S, 5S, and 10S TFTs), (b) representative transfer curve, and (c) trend of the electrical parameters of the devices based on the number of stacking layers.
Table 1. Device parameters (Vth, µFE and SS) for the 1S, 3S, 5S, and 10S TFTs.
Figure 2. (a) STEM image, (b) EDS mapping image (2-D) of Al and In, (c) vertical EDS line scan (1-D) of Al, In, Ga and Zn in a 10-stack IGZO/Al2O3 layer.
Figure 3. (a) 2-D and (b) 1-D distributions of the simulated current density under the operational state (VGS: 10 V, VDS: 0.1 V) based on multi-channel TFT (1S, 3S, 5S and 10S TFTs).
Figure 4. Energy band and enlarged conduction band edge in the gate insulator (SiO2) and IGZO/Al2O3 under the operational state (VGS: 10 V, VDS: 0.1 V) for (a) 1S, (b) 3S, (c) 5S, and (d) 10S TFTs.
Table 2. Potential decomposition under the operational state (VGS: 10 V and VDS: 0.1 V) in the gate insulator (SiO2) and multilayer (IGZO and Al2O3).