Performance and accuracy of hardware-oriented native-, emulated- and mixed-precision solvers in FEM simulations

Abstract

In this survey paper, we compare native double precision solvers with emulated- and mixed-precision solvers of linear systems of equations as they typically arise in finite element discretisations. The emulation utilises two single float numbers to achieve higher precision, while the mixed precision iterative refinement computes residuals and updates the solution vector in double precision but solves the residual systems in single precision. Both techniques have been known since the 1960s, but little attention has been devoted to their performance aspects. Motivated by changing paradigms in processor technology and the emergence of highly-parallel devices with outstanding single float performance, we adapt the emulation and mixed precision techniques to coupled hardware configurations, where the parallel devices serve as scientific co-processors. The performance advantages are examined with respect to speedups over a native double precision implementation (time aspect) and reduced area requirements for a chip (space aspect).

The paper begins with an overview of the theoretical background, algorithmic approaches and suitable hardware architectures. We then employ several conjugate gradient (CG) and multigrid solvers and study their behaviour for different parameter settings of the iterative refinement technique. Concrete speedup factors are evaluated on the coupled hardware configuration of a general-purpose CPU and a graphics processor. The dual performance aspect of potential area savings is assessed on a field programmable gate array (FPGA). In the last part, we test the applicability of the proposed mixed precision schemes with ill-conditioned matrices. We conclude that the mixed precision approach works very well with the parallel co-processors gaining speedup factors of four to five, and area savings of three to four, while maintaining the same accuracy as a reference solver executing everything in double precision.

Keywords:

• Mixed precision iterative refinement
• Emulated precision
• Graphics hardware
• Reconfigurable hardware
• Large sparse linear equation systems
• FEM

Acknowledgements

We would like to thank the feast developers, Christian Becker, Sven Buijssen, Matthias Grajewski, Susanne Kilian and Hilmar Wobker for their patience and invaluable support. The ATI and NVIDIA developer support helped us to sort out issues with the rounding modes in the emulated double–single floating point formats. This research has been partly supported by a Max Planck Center for Visual Computing and Communication fellowship and by the German Science Foundation (DFG), project TU102/22-1.