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Research Article

The extended model predictive-sliding mode control of three-level AC/DC power converters with output voltage and load resistance variations

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Pages 127-137 | Received 17 Aug 2020, Accepted 21 Jan 2021, Published online: 09 Feb 2021

Figures & data

Figure 1. System general diagram.

Figure 1. System general diagram.

Figure 2. Three-level AC/DC converter.

Figure 2. Three-level AC/DC converter.

Figure 3. Voltage vectors representation using the Clarke transformation (αβ coordinate system).

Figure 3. Voltage vectors representation using the Clarke transformation (αβ coordinate system).

Figure 4. The system Block diagram of EMPSMC scheme.

Figure 4. The system Block diagram of EMPSMC scheme.

Figure 5. The system Algorithm of EMPSMC Scheme.

Figure 5. The system Algorithm of EMPSMC Scheme.

Figure 6. Trajectory Plot like any sliding action into SMC.

Figure 6. Trajectory Plot like any sliding action into SMC.

Table 1. Parameter of converter.

Figure 7. The output response of Step Response of EMPSMC schemes.

Figure 7. The output response of Step Response of EMPSMC schemes.

Table 2. Dynamic performance evaluation of EMPSMC and MMPIC

Table 3. System dynamic performance evaluation.

Figure 8. The Output response of the system with EMPSMC plus interference (Disturbance).

Figure 8. The Output response of the system with EMPSMC plus interference (Disturbance).

Figure 9. Output reaction to an unpredicted of dc voltage load demand increase (a) demand load increase (b) demand load decrease.

Figure 9. Output reaction to an unpredicted of dc voltage load demand increase (a) demand load increase (b) demand load decrease.

Figure 10. Output reaction to an unpredicted of dc voltage load demand increase (a) Active power increase (b) Active power decrease.

Figure 10. Output reaction to an unpredicted of dc voltage load demand increase (a) Active power increase (b) Active power decrease.

Figure 11. Output reaction to an unpredicted of dc voltage load demand increase (c) Phase A voltage and current increase (d) Phase A voltage and current decreases under EMPSMC.

Figure 11. Output reaction to an unpredicted of dc voltage load demand increase (c) Phase A voltage and current increase (d) Phase A voltage and current decreases under EMPSMC.

Figure 12. The output response of Step Response of MPPIC schemes.

Figure 12. The output response of Step Response of MPPIC schemes.

Figure 13. The Output response of the system with MPPIC plus interference (Disturbance).

Figure 13. The Output response of the system with MPPIC plus interference (Disturbance).

Figure 14. Comparison of EMPC, MPPIC, and MPC.

Figure 14. Comparison of EMPC, MPPIC, and MPC.