Design and investigation of computation-in-memory based low power hybrid MTJ/CMOS logic gates

Figures & data

Figure 1. SHE + STT device structure and its switching mechanism for (a) AP to P and (b) P to AP configuration (Barla et al., 2021).

Figure 2. Block diagram of CIM structure, comprising of sense amplifier, logic network with MOS tree, and MTJs. MTJ write circuit is used to change the configuration of MTJs.

Figure 3. Various sense amplifier circuits developed to read the information stored in the MTJ pair. MTJ0 and MTJ1 are at opposite states. SS (‘0’ or ‘1’) is used to control the mode of operation. Schematic for (a) conventional SRAM based sense amplifier, (b) ten transistors/one capacitor DCM sense amplifier, (c) PCSA, (d) SPCSA, (e) RESPCSA, (f) ISA. Note that these sense amplifiers are developed for STT MTJs. The same sense amplifier circuits can be used for SHE + STT MTJs as their reading mechanism is same.

Figure 4. Schematic of AWS write circuitry constituting (a) control circuit, (b) write core and (c) self-termination circuit. Direction of I_STT and I_SHE are marked during writing the information bit ‘0’ and ‘1’.

Table 1. Various input signals, intermediate signals, write enabler outputs and the corresponding MTJ states for the AWS circuit.

Input signals			Output signals		MTJ status
EW	Input	ESHE	STTP	STTN	MTJ0	MTJ1
0	$\mathrm{X}$	$\mathrm{X}$	1	0	$\text{NC}$	$\text{NC}$
1	1	1	1	1	Metastable
1	1	0	1	1	$\mathrm{P}$	$\text{AP}$
1	1	0	1	0	$\text{NC}$	$\text{NC}$
1	0	1	0	0	Metastable
1	0	0	0	0	$\text{AP}$	$\mathrm{P}$
1	0	0	1	0	$\text{NC}$	$\text{NC}$

Abbreviations: X: Don’t care condition; NC: No Change.

Figure 5. Hybrid SHE+STT MTJ/CMOS logic gates for CIM structure, showing (a) ISA, (b) MOS tree for: XOR/XNOR, (h) NAND/AND and (g) OR/NOR, (c) logic network, (d) write core, (e) self termination circuit.

Table 2. Truth table for various logic gates along with the corresponding path resistance for the LA and RA current in logic network.

	Inputs		LA resistance	RA resistance	Resistance
Gate type	A	B	(RLA)	(RRA)	comparison	OUT+	OUT-
NOR/OR	0	0	$R_{\mathit{\text{Close}}}+R_{\mathit{\text{AP}}}$	$R_{\mathit{\text{Close}}}+R_P$	RLB > RRB	0	1
	0	1	$R_{\mathit{\text{Close}}}+R_P$	$R_{\mathit{\text{Close}}}+R_{\mathit{\text{AP}}}$	RLB < RRB	1	0
	1	0	$R_{\mathit{\text{Close}}}+R_{\mathit{\text{AP}}}$	$R_{\mathit{\text{Open}}}+R_P$	RLB < RRB	1	0
	1	1	$R_{\mathit{\text{Close}}}+R_P$	$R_{\mathit{\text{Open}}}+R_{\mathit{\text{AP}}}$	RLB < RRB	1	0
NAND/AND	0	0	$R_{\mathit{\text{Open}}}+R_{\mathit{\text{AP}}}$	$R_{\mathit{\text{Close}}}+R_P$	RLB > RRB	0	1
	0	1	$R_{\mathit{\text{Open}}}+R_P$	$R_{\mathit{\text{Close}}}+R_{\mathit{\text{AP}}}$	RLB > RRB	0	1
	1	0	$R_{\mathit{\text{Close}}}+R_{\mathit{\text{AP}}}$	$R_{\mathit{\text{Close}}}+R_P$	RLB > RRB	0	1
	1	1	$R_{\mathit{\text{Close}}}+R_P$	$R_{\mathit{\text{Close}}}+R_{\mathit{\text{AP}}}$	RLB < RRB	1	0
XNOR/XOR	0	0	$R_{\mathit{\text{Close}}}+R_{\mathit{\text{AP}}}$	$R_{\mathit{\text{Close}}}+R_P$	RLB > RRB	0	1
	0	1	$R_{\mathit{\text{Close}}}+R_P$	$R_{\mathit{\text{Close}}}+R_{\mathit{\text{AP}}}$	RLB < RRB	1	0
	1	0	$R_{\mathit{\text{Close}}}+R_P$	$R_{\mathit{\text{Close}}}+R_{\mathit{\text{AP}}}$	RLB < RRB	1	0
	1	1	$R_{\mathit{\text{Close}}}+R_{\mathit{\text{AP}}}$	$R_{\mathit{\text{Close}}}+R_P$	RLB > RRB	0	1

Abbreviations: R_Close: NMOS, ON resistance; R_Open: NMOS, OFF resistance; R_P: P state resistance of MTJ; R_AP: AP state resistance of MTJ.

Table 3. SHE + STT MTJ parameters set during the simulation. Rest of the parameters are retained as mentioned in ref. (Wang et al., 2015).

Parameter	Description	Value
tsl	Free layer thickness	0.7 nm
tox	MgO barrier thickness	0.85 nm
TMR	TMR ratio under zero bias voltage	200%
shape	MTJ Surface shape	circle
$\mathrm{a}$	MTJ Surface length	32nm
$\mathrm{b}$	MTJ Surface width	32nm
$\mathrm{r}$	MTJ Surface radius	16nm
$\mathrm{w}$	Heavy-metal width	40nm
$\mathrm{d}$	Heavy-metal thickness	3nm
$\mathrm{l}$	Heavy-metal length	60nm
σTMR	Standard deviation of TMR	3% of TMR
${\sigma }_{t_{\mathit{\text{sl}}}}$	Standard deviation of tsl	3% of tsl
${\sigma }_{t_{\mathit{\text{ox}}}}$	Standard deviation of tox	3% of tox

Table 4. Write energy consumption of CW and AWS write circuits.

	Writing ‘1’	Writing ‘0’	Redundant write	Average
CW energy/bit	$1.43\text{pJ}$	$1.43\text{pJ}$	$1.43\text{pJ}$	$1.43\text{pJ}$
AWS energy/bit	$51.63\text{fJ}$	$51.58\text{fJ}$	$37.49\text{fJ}$	$46.93\text{fJ}$

Figure 6. Waveform for the AWS write circuit showing (a) input (b) write enable (WE), (c) SHE signal (ESHE), (d) state of MTJ0 and (e) MTJ1, (f) node N voltage, output of (g) I4 inverter (EWT) and (h) write completion detector (EWRT),control circuit outputs (i) STTP and (j) STTN, (k) AWS I_STT and (l) conventional I_STT.

Figure 7. Various input and output waveforms for different hybrid logic gates. Between T1 to T3, one of the condition wherein information bit ‘1’ being written into the MTJ pair is shown. Initially MTJ pair (input B) is stored with information ‘0’. At T1, writing the bit ‘1’ into the MTJ pair was initiated. At time T2, writing the bit ‘1’ is complete. Due to the CM and AWS process, in AWS gates the I_STT current is stopped at T2 whereas in CW gate the I_STT continues to flow till T3. So T3-T2 is the time for which power is saved with ISA + AWS gates. In the pre-charge phase (SS = 0); ISA + AWS gate’s both output and its complement are at Vdd-Vth, whereas for CW gates it is Vdd.

Figure 8. Comparison of (a) read circuitry (b) write circuitry and (c) total (read + write circuitry) power dissipation for CW and ISA + AWS logic gates.

Table 5. Performance comparison between hybrid CW and ISA + AWS logic gates.

	CW	ISA + AWS	CW	ISA + AWS	CW	ISA + AWS
	AND/NAND		OR/NOR		XOR/XNOR
Auto-write-stopping	No	Yes	No	Yes	No	Yes
Continuous monitoring	N/A	Yes	N/A	Yes	N/A	Yes
Area($\mu m^2$) ${}^{*}$	334.86	437.45	334.86	437.45	334.87	437.46
Worst-case read delay(ps) ^a	132.79	96.39	91.13	78.91	91.41	71.95
Worst-case write delay(ps) ^b	268.04	355.55	267.9	354.7	268.1	357.64
Read circuitry power dissipation(nW) ^c	123.2	88.86	125.6	107.6	143.4	110.5
Control circuit power dissipation(nW) ^d	91.87	410.3	91.77	414.4	91.79	413
Writing core power dissipation(μW) ^e	4.55	1.84	4.55	1.84	4.55	1.84
Write circuitry power dissipation(μW) ${}^{d+e}$	4.64	2.25	4.64	2.25	4.64	2.25
Total power dissipation(μW) ${}^{c+d+e}$	4.77	2.36	4.77	2.36	4.79	2.36
Read power delay product(aJ) ${}^{a*c}$	16.35	8.56	11.44	8.49	13.1	7.95
Write power delay product(fJ) ${}^{b*(d+e)}$	1.24	0.78	1.24	0.79	1.24	0.8

${}^{*}$Area is obtained by multiplying W and L of the MOS transistors.

Figure 9. Comparison of worst case (a) read and (b) write delay for CW and ISA + AWS logic gates.

Figure 10. Worst case (a) read and (b) write PDP comparison between CW and ISA + AWS logic gates.

Figure 11. Dependence of read circuitry’s power dissipation, delay and PDP on size of PD transistor for ISA + AWS (a) AND/NAND, (b) OR/NOR, and (c) XOR/XNOR logic gates.

Figure 12. Variation of write circuitry and total power dissipation with the respect to width of the write core transistor.

Figure 13. MC simulation showing the power dissipation in CW: AND/NAND (a) LIM circuitry, (b) Write circuitry, (c) total power; OR/NOR (d) LIM circuitry, (e) Write circuitry, (f) total total; XOR/XNOR (g) LIM circuitry, (h) Write circuitry, (i) total power.

Figure 14. MC simulation showing the power dissipation in ISA + AWS: AND/NAND (a) LIM circuitry, (b) Write circuitry, (c) total power; OR/NOR (d) LIM circuitry, (e) Write circuitry, (f) total total; XOR/XNOR (g) LIM circuitry, (h) Write circuitry, (i) total power.

Table 6. MC simulation revealing the various power dissipation for CW and ISA + AWS logic gates with 200 iterations.

Circuit type	Power dissipation	Min	Max	Mean	Std deviation
	LIM circuitry (nW)	111.1	135.4	123.2	4.22
CW	Control circuit (nW)	89.35	94.74	91.92	1.11
AND/NAND	Writing core (μW)	4.14	4.88	4.56	0.136
	Write circuitry (μW)	4.23	4.98	4.65	0.136
	Total (μW)	4.36	5.1	4.77	0.136
	LIM circuitry (nW)	77.85	99.37	88.6	3.67
ISA + AWS	Control circuit (nW)	320.3	464.1	389.1	32.15
AND/NAND	Writing core (μW)	0.768	4.82	2.7	1.5
	Write circuitry (μW)	1.19	5.18	3.09	1.47
	Total (μW)	1.28	5.28	3.18	1.48
	LIM circuitry (nW)	112.8	137.5	125.4	4.24
CW	Control circuit (nW)	89.3	94.56	91.82	1.09
OR/NOR	Writing core (μW)	4.16	4.88	4.55	0.135
	Write circuitry (μW)	4.25	4.97	4.65	0.135
	Total (μW)	4.38	5.1	4.77	0.136
	LIM circuitry (nW)	86.08	518.6	132.2	69.44
ISA + AWS	Control circuit (nW)	319.5	468.3	389.4	37
OR/NOR	Writing core (μW)	0.772	4.81	2.74	1.49
	Write circuitry (μW)	1.18	5.17	3.13	1.4
	Total (μW)	1.29	5.3	3.26	1.5
	LIM circuitry (nW)	128.2	158.1	143.3	5.25
CW	Control circuit (nW)	89.14	94.48	91.83	1.06
XOR/XNOR	Writing core (μW)	4.25	4.95	4.54	0.135
	Write circuitry (μW)	4.34	5.05	4.63	0.136
	Total (μW)	4.47	5.2	4.77	0.137
	LIM circuitry (nW)	89.22	576.6	135.7	68.35
ISA + AWS	Control circuit (nW)	315.8	478.5	386.7	38.24
XOR/XNOR	Writing core (μW)	0.950	4.85	2.77	1.5
	Write circuitry (μW)	1.33	5.21	3.15	1.47
	Total (μW)	1.42	5.41	3.29	1.5

Barla, P., Joshi, V. K., & Bhat, S. (2021). Spintronic devices: A promising alternative to CMOS devices. Journal of Computational Electronics, 20(2), 805–837. https://doi.org/10.1007/s10825-020-01648-6

 Web of Science ®Google Scholar

Wang, Z., Zhao, W., Deng, E., Klein, J.-O., & Chappert, C. (2015). Perpendicular-anisotropy magnetic tunnel junction switched by spin-Hall-assisted spin-transfer torque. Journal of Physics D: Applied Physics, 48(6), 065001. https://doi.org/10.1088/0022-3727/48/6/065001

 Web of Science ®Google Scholar

Data availability statement

Data available on request from the authors.