Fabrication and Electrical Characteristics of P(VDF-TrFE) Films on Si(100) Substrates Using Cyanoethyl Pullulan Buffer Layers

Abstract

We fabricated a metal-ferroelectric-insulator-semiconductor structure using a poly(vinylidene fluoride trifluorethylene) as a ferroelectric layer and a cyanoethyl pullulan as an insulating buffer layer for the first time. The CEP thin films were deposited on Si substrate by using a sol-gel method. The coated P(VDF-TrFE) films on CEP/Si structure were crystallized. For the Au/P(VDF-TrFE)/CEP/Si structure, the capacitance-voltage characteristics showed hysteresis loops, the memory window width was about 4.6V at a bias sweep range of ±5V. The leakage current density was about 5.5 × 10⁻⁷ A/cm² at 5V for the thick film from the 5 wt% solution.

Keywords:

• MFIS; ferroelectric; P(VDF-TrFE); CEP

Funding

This research was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2010-0021507).