Evaluation of C-V characteristic of MFS capacitor considering effects of interface traps

Abstract

An improved model combining the quantum mechanical model, dipole switching theory with silicon physics of MOS capacitor was proposed to investigate the effects of interface traps on the surface potential of semiconductor, C-V characteristic and memory window of MFS capacitor. The simulated results show that both -V and C-V curves shift toward the positive-voltage direction and memory window becomes worse as the density of interface trap states increases. It is expected that this work can give some guidance to the experimental researchers for the design and characteristic improvement of MFS devices.

KEYWORDS:

• C-V characteristic
• interface traps
• MFS capacitor
• model

Funding

This work was supported by NNSF of China (51502087), Hunan Provincial Natural Science Foundation of China (14JJ6040, 14JJ6041, 2015JJ6024), Scientific Research Fund of Hunan Provincial Education Department (15B056, 14B041, 14K029) and Start-up Fund for doctorate of Hunan Institute of Engineering.