Systolic neural algorithms

Abstract

This paper describes the three neural network training algorithms that have been implemented in the systolic array processor [1], It describes the individual stages of each algorithm, along with any requirements for constant data values within the array, as well as details for any instructions that are ‘locked’ into a PE for perpetual execution. Dataflow diagrams within the systolic array for each stage of each algorithm, showing the implications of each calculation and the implied direction of the execution flow, are also shown and timing information for each stage of each algorithm are also given.

Keywords:

• Systolic array
• learning algorithms
• back propagation
• Kohonen
• counter propagation

C.R. Categories:

• I5.1
• F1.1
• C1.3