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Abstract
Compact physics/process-based model for threshold voltage in double-gate devices is presented. Predominant short-channel effects for double-gate devices, which are drain-induced barrier lowering (DIBL) and short-channel-induced barrier lowering (SCIBL), are physically analysed and modeled to be applicable to SPICE-compatible circuit simulators. The short-channel models are also developed for bulk-Si device and compared to those of double-gate devices. The validity and predictability of the models are demonstrated and confirmed by numerical device simulation results for extremely scaled L eff = 25 nm double-gate devices and bulk-Si device.