Precise estimation of crosstalk in multiline circuits

Abstract

With advances in VLSI technology, increasing wire density causes coupled-noise or cross-talk, which may lead to critical delays or logic malfunctions. Traditional SPICE simulators are not time-efficient estimators of crosstalk, hence alternatives are sought to ensure acceptable signal integrity in a limited design cycle time. This work proposes a novel and accurate crosstalk noise estimation method in the presence of multiple lines for use in design automation tools. It offers a complete multiline noise model, for the first time, by representing active and passive aggressors simultaneously on the victim line. In the model, active aggressors are represented by current sources and passive aggressors are accurately modelled as equivalent capacitances. Realistic exponential aggressor waveform and resistive shielding effect is all considered. This approach allows to obtain a general noise model that considers the effect of many active and passive aggressors and general formulas derived can easily be applied to real cases. Results show an average error of 4.4% for the noise peak and 6.8% for the width with respect to HSPICE while allowing for very fast analysis.

Keywords:

• Crosstalk estimation
• Layout verification
• Interconnects
• Multiline