Improved CMOS continuous programmable divider

Abstract

A programmable divider with improved prescaler structure is presented. On the basis of the timing-requirement of the trigger, the logic structure of the dual-modulus 16/17 prescaler is analysed and optimised carefully. For which synchronism divider is positive edge-triggered, asynchronous divider is negative edge-triggered and a three-input NAND gate is used for controlling feedback logic. It helps to improve the speed of the prescaler about three times as much as the conventional structure using the same modules. It is fabricated in 0.25 μm standard CMOS process. The measured results show that the chip can work well with 80 to 900 MHz VCO output, achieving frequency dividing from 256 to 32767, and current dissipation of the full divider is 4.2 mA with 3.3 V supply, of which the dual-modulus prescaler is only 1.1 mA.

Keywords:

• trigger
• continuous programmable divider
• dual-modulus
• prescaler
• synchronous
• asynchronous