Low cost high throughput pipelined architecture of 2-D 8 × 8 integer transforms for H.264/AVC

Abstract

In this article, we present the implementation of high throughput two-dimensional (2-D) 8 × 8 forward and inverse integer DCT transform for H.264. Using matrix decomposition and matrix operation, such as the Kronecker product and direct sum, the forward and inverse integer transform can be represented using simple addition operations. The dual clocked pipelined structure of the proposed implementation uses non-floating point adders and does not require any transpose memory. Hardware synthesis shows that the maximum operating frequency of the proposed pipelined architecture is 1.31 GHz, which achieves 21.05 Gpixels/s throughput rate with the hardware cost of 42932 gates. High throughput and low hardware makes the proposed design useful for real time H.264/AVC high definition processing.

Keywords:

• DCT
• dual clock architecture
• H.264/AVC
• IDCT
• integer transform

Acknowledgements

This work was supported in parts by the IDEC and Konkuk University.