A novel reversible carry-selected adder with low latency

ABSTRACT

Reversible logic is getting more and more attention in quantum computing, optical computing, nanotechnology and low-power complementary metal oxide semiconductor designs since reversible circuits do not loose information during computation and have only small energy dissipation. In this paper, a novel carry-selected reversible adder is proposed primarily optimised for low latency. A 4-bit reversible full adder with two kinds of outputs, minimum delay and optimal quantum cost is presented as the building block for $n$-bit reversible adder. Three new reversible gates NPG (new Peres gate), TEPG (triple extension of Peres gate) and RMUX21 (reversible 2-to-1 multiplexer) are proposed and utilised to design efficient adder units. The secondary carry propagation chain is carefully designed to reduce the time consumption. The novelty of the proposed design is the consideration of low latency. The comparative study shows that the proposed adder achieves the improvement from 61.46% to 95.29% in delay over the existing designs.

KEYWORDS:

• Reversible
• adder
• quantum
• carry-selected
• low latency
• delay

Disclosure statement

No potential conflict of interest was reported by the authors.

Additional information

Funding

This work is supported by the National Natural Science Foundation of China [grant number 61462026]; the project of Science and Technology of Jiangxi province [grant number 20141BDH80007]; the item of science and technology awarded by Education Bureau of Jiangxi Province [grant number GJJ14395]; the project of East China Jiaotong University [grant number 14XX03].