High-level design flow and environment for FPGA-based dynamic partial reconfiguration

ABSTRACT

The main motivation of this paper is related to the lack of a high-level design flow for field-programmable gate array (FPGA) partial dynamic reconfiguration management. Our contribution consists in proposing a high-level add-on methodology to the Xilinx’s design flow for dynamic partial reconfiguration (DPR). The main objective is to give an abstract view of the developed application in order to facilitate the designer task. The suggested design flow offers an application-centric view on dynamic reconfiguration designs, which permits simplifying the optimisation and generation of such designs. A new formulation of the reconfigurable modules’ mapping process is put forward. This allows a design space exploration so as to find the convenient number of reconfigurable regions and their sizes as well as the reconfiguration sequence. A new tool was proposed to support our methodology by allowing creating and synthesising graphical models of the developed application. We introduce a new block diagram to represent this latter and a sequence model that can be used for the design optimisations. To validate the proposed DPR design environment, two application examples are given at the end of the paper. They demonstrate the usefulness of the suggested models and methods.

KEYWORDS:

• Dynamic partial reconfiguration
• FPGA
• design flow and environment
• self-reconfiguration
• SOC

Disclosure statement

No potential conflict of interest was reported by the authors.​​​​​​​