Energy-Efficient approximate compressor design for error-resilient digital signal processing

ABSTRACT

Approximate computing can be considered a well-promising method for improving the critical performance criteria, such as latency and power consumption at the cost of accuracy penalty. The (4,2) compressor is a vital block at the heart of various arithmetic circuits like multipliers. This paper proposed two approximate (4,2) compressors with power and delay improvements with the error-correcting module. The simulation results based on 7 nm FinFET technology show that the proposed designs compared to the most efficient related approximate (4,2) compressors, reduce delay, power, and energy consumption. Furthermore, according to the comprehensive Monte Carlo simulations, the robustness of the proposed designs in the presence of significant FinFET process variations compared to the previous compressors is proven. In addition, an image multiplication process assesses the effectiveness of the proposed approach in the qualitative assessment of the inexact multiplier. The obtained results indicate acceptable accuracy of inexact multiplier based on the proposed approximate (4,2) compressor.

KEYWORDS:

• Arithmetic circuits
• approximate computing
• compressor
• majority logic
• digital signal processing

Disclosure statement

No potential conflict of interest was reported by the author(s).