Cost-efficient method for inverter reduction and proper placement in quantum-dot cellular automata

ABSTRACT

The Quantum-dot Cellular Automata (QCA), an emerging technology, is observed to be the most viable solution to current CMOS. It is capable of finding solutions to challenges, like high power consumptionand device density. The elementary logic primitives are the majority gate, inverter and wire. In QCA, two different event cell orientations for the realisation of the inverter are available, where the diagonally oriented structure (DOS) is mostly utilised in logic synthesis. However, considering the cell misalignment and displacement, the DOS prevails with a more stable polarised output. But the use of DOS increases cell count which increases the area of the circuit. So, it is desirable to minimise the inverter in a circuit due to the non-availability of the simple logic unit of the inverter. In this paper, two algorithms are proposed for the synthesis of cost-efficient QCA circuits from any boolean function to minimize logic primitives. The proposed role-based mechanism for boolean function synthesis results in the reduction of inverter gate, circuit size, QCA cost and power dissipation. The efficiency of the proposed algorithms has been verified with the realization of standard functions, adders and symmetric functions. A significant improvement in inverter reduction has been reported.

KEYWORDS:

• Quantum-dot cellular automata
• QCA inverter
• inverter reduction
• inverter placement
• QCADesigner

Acknowledgment

This work is sponsored by the Young Faculty Research Fellowship (YFRF) of the Visvesvaraya Ph.D. scheme through grant number MLA/MUM/GA/10(37)B.

Disclosure statement

No potential conflict of interest was reported by the author(s).

Additional information

Funding

The work was supported by the Young Faculty Research Fellowship (YFRF) of the Visvesvaraya Ph.D. scheme [MLA/MUM/GA/10(37)B].