Fault-Tolerant Analysis of 5-level Modified T-type and Packed U Cell MLI

ABSTRACT

In this work, 5-level modified T-type and modified Packed-U-Cell (PUC) multilevel inverter (MLI) topologies are designed with reduced device count for the reliability analysis of the MLI under faulty conditions. This work aims to incorporate the fault either by loss of an individual switch or due to the loss of a single h-bridge leg. Also, the proposed T-type and PUC inverter have an inherent self-voltage balancing capability that reduces the complexity and enhances the circuit’s reliability. First, the proposed topologies are simulated using Matlab/Simulink environment, and the results obtained are then compared with the conventional MLI. Finally, both MLIs are experimentally tested on a laboratory prototype as a proof of concept to validate the analytical developments.

KEYWORDS:

• Fault-tolerant
• T-type
• Packed U Cell
• multilevel inverter
• reliability

Acknowledgements

The work reported herein was supported financially by the Ministerio de Ciencia e Innovación (Spain) and the European Regional Development Fund, under the Research Grant WindSound project (Reference: PID2021-125278OB-I00). The authors extend their appreciation to the Researchers Supporting Project at Universiti Teknologi Malaysia (UTM), Malaysia (UTMFR: Q.J130000.3823.23H05 and UTMER: Q.J130000.3823.31J06). The authors extend their appreciation to Intelligent Prognostic Private Limited Delhi, India for providing technical support in this research work.

Disclosure statement

No potential conflict of interest was reported by the author(s).

Additional information

Funding

This work was supported by the Ministerio de Ciencia e Innovación [PID2021-125278OB-I00].