Enhancing the design of a two-stage CMOS operational amplifier utilising the Bat Algorithm

ABSTRACT

The increasing demand for high-performance two-stage CMOS Op-Amps in electronic, communications, and biomedical applications necessitates their operation with wide bandwidth, high voltage gain, and low power consumption. By leveraging the Bat Algorithm global search and local exploration capabilities, the study demonstrates a significant improvement in the amplifier’s overall performance. This design of a two-stage CMOS Op-Amp using 0.18 µm TSMC technology, powered by a ± 1.8 V supply voltage. The simulation outcomes were gathered using the PSPICE software (version 17.4). These design strategies prove highly efficient, achieving high gain, high frequency, and low power consumption. Additionally, the paper showcases the execution and simulation results of a two-stage CMOS Op-Amp based on the Bat Algorithm, utilising MATLAB for this purpose. The employment of the BA results in substantial enhancements in performance metrics. Specifically, the Unity Gain Bandwidth sees a doubling in its value, the voltage gain rises by 20%, power consumption falls by 39.1%, and the Common Mode Rejection Ratio improves by 20% compared to a two-stage CMOS Op-Amp designed without the BA. The findings underscore the BA potency as a robust optimisation method for boosting the performance of a two-stage CMOS Op-Amp.

KEYWORDS:

• Two-stage CMOS Op-Amp
• Bat Algorithm
• UGB
• CMRR
• voltage gain

Acknowledgements

I would like to thank Prof. Dr. Hassan Jasim Motlak for his support this work.

Disclosure statement

No potential conflict of interest was reported by the author(s).