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ABSTRACT
An all-CMOS ternary J-K triflop (ternary flip-flop) is presented. It has three ternary logic outputs with levels 0, 1 and 2, representing present, future and past output states, and has preset facilities to obtain any one of these three logic levels as is required at the output. This ensures great flexibility for ternary sequential circuit design (ternary shift registers, counters, latches, etc.) and can as such be considered as a universal memory element for ternary logic design.