Analysis of a borderless fab using interoperating AutoSched AP models

Abstract

Semiconductor front-end manufacturing is a complex process involving a large number of fabrication steps that require capital-intensive equipment. To address shortages that can arise in individual wafer fabs in situations such as machine breakdowns or unexpected surge in demand for some products, the concept of a borderless fab is presented in this paper. In a borderless fab, multiple wafer fabs pool their capacity together, allowing movement of partially completed wafer lots from one fab to another. This enables the redistribution of workload to other similar resources in alternative fabs to maintain the targeted production cycle time. For the purpose of this study, two wafer fabs within close proximity and with similar processing capabilities were modeled using the AutoSched AP (ASAP) simulation package. Instead of creating one single large model, each wafer fab is modeled as an individual ASAP model. Simulation is executed on two computers interconnected by a local area network. The High Level Architecture (HLA) standard is adopted to enable the distributed execution. A novel time synchronization algorithm is proposed that is approximately ten times more efficient compared to conventional algorithms. The interoperating ASAP models were then used to investigate the effect of different lot batching sizes on lot transfer frequency and the average production cycle time in a borderless fab scenario. The experimental results show how an optimal operating point for lot batching size can be obtained from the intersection point of normalized contradictory performance indices. The operating point yields a balance between the number of lot movements between fabs and average cycle time.

Keywords:

• Distributed simulation
• Borderless fab
• Capacity sharing
• Outsourcing

Acknowledgements

The authors would like to thank Professor Leon F. McGinnis from Georgia Institute of Technology, Professor John W. Fowler from Arizona State University, Dr Simon Taylor from Brunel University, Dr Malcolm Yoke Hean Low from Singapore Institute of Manufacturing Technology, Mr Hiap Keong Tan and Mr Sip Khean Lieu from Chartered Semiconductor Manufacturing Ltd for their valuable contribution in this work.

Notes

†Potential event is defined as an event that potentially can trigger an external timestamped message.

‡PEL(a, b)—potential event list for flow a at step b.