Integrating a decomposition procedure with problem reduction for factory scheduling with disruptions: a simulation study

Abstract

Dispatching rules are widely used in industry because schedules obtained from optimization procedures can be difficult to implement in the face of executional uncertainties. Barua et al. (Barua, A., Narasimhan, R., Upasani, A. and Uzsoy, R., Implementing global factory schedules in the face of stochastic disruptions. Int. J. Prod. Res., 2005, 43(4), 793–818) implement global schedules obtained from an optimization-based heuristic using a dispatching rule, and outperform myopic dispatching rules in the face of disruptions. However, the computation of the global schedules is still time-consuming for realistic instances. Upasani et al. (Upasani, A., Uzsoy, R. and Sourirajan, K., A problem reduction approach for scheduling semiconductor wafer fabrication facilities. IEEE Trans. Semicon. Manuf., 2006, 19, 216–225) develop a problem reduction scheme based on load disparity between work centres, and report significant reduction in CPU times with minimal loss of solution quality in deterministic experiments. In this paper we integrate the problem-reduction scheme to obtain global schedules with the dispatching approach of Barua et al. (Barua, A., Narasimhan, R., Upasani, A. and Uzsoy, R., Implementing global factory schedules in the face of stochastic disruptions. Int. J. Prod. Res., 2005, 43(4), 793–818) in a multi-product environment with stochastic machine breakdowns and job arrivals. A simulation model of a scaled-down wafer fabrication facility is used to evaluate the performance of the proposed procedures. Results show that the integrated procedure outperforms the benchmark dispatching rules while significantly reducing computation times.

Keywords:

• Decomposition heuristics
• Job-shop scheduling
• Global schedules
• Rescheduling
• Semiconductor wafer fab scheduling
• Simulation

Acknowledgements

This research was partially supported by the National Science Foundation under Grant Number DMI-0085047, by an equipment grant from Intel Corporation and a software grant from Symix Corporation.