Inter-arrival time patterns in manufacturing systems with main and side loops

Abstract

Manufacturing systems with main and side loops that employ asynchronous, track-based workpiece holder transport with decentralised control generally allow arbitrarily small distances between workpiece holders, so that their state space is partly continuous. The considered systems show complex inter-arrival time distributions that can reduce system capacity when multiple routes share common tracks. This paper presents an analytical approach to modelling this inter-arrival time behaviour that distinguishes between different zones in parameter space by associating each zone with one specific queueing situation. For each queueing situation, a recursively defined sequence is set up that represents the inter-arrival times of workpiece holders. Two of these sequences yield inherently different types of turbulence that form characteristic patterns in phase diagrams. The emergence of these patterns is validated using a deterministic discrete-event simulation of an assembly system. A synchronisation methodology is introduced that limits the number of different inter-arrival times. The employed queueing–situational decomposition avoids sophisticated mathematical modelling and provides an easy explanation for the root causes of the emerging turbulence. It thereby helps the manufacturing system designer avoid the resulting decrease in capacity and reliability.

Keywords:

• manufacturing systems
• design
• inter-arrival time patterns
• turbulence

Notes

Note

1. The notation employed in this paper consists of the main character as the basic property (e.g. time), the lower right index as the type of basic property, the upper left index as the location of the property and the lower left as the respective route that the property refers to. For example, the notation refers to the basic property time of the type inter-arrival time at the location fork in front of the bottleneck side loop, only considering workpiece holders that follow the main-loop route.