A batching and scheduling algorithm for the diffusion area in semiconductor manufacturing

Abstract

This paper proposes an efficient heuristic algorithm for solving a complex batching and scheduling problem in a diffusion area of a semiconductor plant. Diffusion is frequently the bottleneck in the plant and also one of the most complex areas in terms of number of machines, constraints to satisfy and the large number of lots to manage. The purpose of this study is to investigate an approach to group lots in batches and to schedule these batches on machines. The problem is modelled and solved using a disjunctive graph representation. A constructive algorithm is proposed and improvement procedures based on iterative sampling and Simulated Annealing are developed. Computational experiments, carried out on actual industrial problem instances, show the ability of the iterative sampling algorithms to significantly improve the initial solution, and that Simulated Annealing enhances the results. Furthermore, our algorithm compares favourably to an algorithm reported in the literature for a simplified version of our problem. The constructive algorithm has been embedded in software and is currently being used in a semiconductor plant.

Keywords:

• batch scheduling
• disjunctive graph
• heuristics
• semiconductor manufacture
• simulated annealing

Acknowledgements

This work forms part of the MEDEA + European project HYMNE (High Yield driven MaNufacturing Excellence in sub 65 nm CMOS), partly funded by the ‘Ministère de l'Économie, de l'Industrie et de l'Emploi’ (French Ministry of Economy, Industry and Employment).

Notes

Note

1. Specifications on a process as to how it should be executed on a tool. This pertains to the requirements of maintaining a proper temperature, pressure, and metal composition, among other things.