Incorporating engineering process improvement activities into production planning formulations using a large-scale wafer fab model

Abstract

In most semiconductor wafer fabrication facilities (wafer fabs), both production and engineering lots share the same expensive equipment. Production lots will be shipped to customers whereas engineering lots are used to support production and process development efforts. While production activities might lead to large revenue, engineering activities result in increased future output. In the present paper, we propose three different production planning formulations. The first formulation assumes a reduced available capacity for production due to engineering activities. Costs for production products are minimised. The second formulation is based on the idea that aggregated demand is available for engineering activities for the entire planning window. Costs for production and engineering products are minimised. Learning effects are incorporated to model the capacity increase due to engineering activities. The third model assumes that demand information for engineering activities is available only for the first period. In addition to learning effects, forgetting effects are modelled to provide an incentive to plan releases of engineering lots in later periods. Costs for production and engineering products and forgetting effects are minimised. The performance of the production planning models is assessed using a simulation model of a large-scale wafer fab including specific dispatching strategies to deal with production and engineering lots. The simulation results demonstrate that the second model slightly outperforms the third one when a rolling horizon approach is taken, while the second model provides significantly higher profit than the first one.

Keywords:

• production planning
• engineering processes
• continuous improvement
• simulation experiments

Acknowledgement

The authors would like to thank Hans Ehm, Infineon Technologies AG and Volker Schmalfuß, X-FAB Foundries AG for useful information on engineering lots in semiconductor manufacturing. This research was partially funded by the European Commission Seventh Framework Programme FP7/2007-2013 under the project ARUM, grant agreement no 314056. The authors gratefully acknowledge the provided financial support.