Mismatch address indexing for test data compression

Abstract

Test data volume is a major problem encountered in System-On-Chip testing. One solution to this problem is to use compression techniques to reduce the test data volume. In this article, we propose a mismatch address indexing method for test data compression. This method is based on the observation that in a well-sorted test sequence, the difference bits between consecutive test vectors are very few. If the position of each difference bit is recorded, the successive test vector can be reconstructed from its precedent test vector. However, instead of indicating each individual difference bit, each mismatch group consisting of a series of difference bits is indicated. Two parameters: length and address are used to encode each mismatch group. Experimental results show good compression can be achieved. Also, good adaptability is demonstrated for today's practical-scale circuits.

Keywords:

• test data compression
• test vector reordering
• Hamiltonian path

Acknowledgement

The authors gratefully acknowledge the comments of the referees of this article.