Polynomial Basis Multiplier Using Cellular Systolic Architecture

ABSTRACT

In this study, we present a polynomial basis multiplication architecture based on cellular systolic hardware architecture for Montgomery multiplication over Galois fields by adopting a qualified Montgomery factor which is highly suitable for the design on our structures. At first, we propose a parallel computation algorithm which operates two independent computations. The algorithm is efficiently designed by reordering the sequence of the terms on the polynomial. Second, we construct an ideal architecture which is composed of two independent parts. Our architecture is possible to compute two parts simultaneously. Each part is composed of same cell structures so that it is easy to be generalized and scalable. Finally, we obtain a time-saved architecture in a large degree with high scalability.

Keywords:

• Circuit design
• Multiplication architecture
• Galois fields
• Polynomial basis
• Montgomery factor

ACKNOWLEDGEMENTS

This research was supported by Ministry of Culture, Sports and Tourism (MCST) and Korea Creative Content Agency (KOCCA) in the Culture Technology (CT) Research and Development Program. This research was also supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT & Future Planning (2011-0014977).

Additional information

Notes on contributors

Kee-Won Kim

Kee-Won Kim received his B.Sc. degree in Computer Science & Statistics from Kyungsung University in 1999 and the M.E. degree in Computer Engineering from Kyungpook National University in 2001, Republic of Korea. He received the Ph.D. degree in Computer Engineering from Kyungpook National University in 2006, Republic of Korea. Currently, he is an assistant professor at College of Convergence Technology and Institute of Media Content, Dankook University, Republic of Korea. His current research interests are cryptography, VLSI, network security, quantum-dot cellular automata and bigdata security.

E-mail: [email protected]

Jun-Cheol Jeon

Jun-Cheol Jeon received B.S. degree in Computer Engineering from Kumoh National Institute of Technology, Korea in 2000. He received the M.S. and Ph.D. degree in computer engineering from Kyungpook National University, Korea in 2003 and 2007 respectively. He is currently a professor of department of computer engineering at Kumoh National Institute of Technology in Korea. His major research interests include cryptography, crypto-coprocessor design, quantum-dot cellular automata, and quantum cryptography.

E-mail: [email protected]