Design of a DPSK Modem Using CORDIC Algorithm and Its FPGA Implementation

ABSTRACT

In the present work, a power efficient differential phase shift keying (DPSK) modem has been implemented using COordinate Rotation DIgital Computer (CORDIC) algorithm in hardware descriptive language (VHDL) code. Here, CORDIC algorithms are used to generate the carrier in the modulator and to implement the multiplier in the demodulator. Carrier generator on the same chip minimizes the effect of noise significantly. Single-chip implementation provides a low power DPSK modem operating with high frequency which is suitable for wireless communication system. The CORDIC algorithm based DPSK modem is found to be a much efficient system in terms of reduced hardware cost, improved performance, and included flexibility. Importance of portable field programmable gate array (FPGA) based device for wireless communication system and system on single chip is now growing rapidly. In this context, the proposed modem provides an efficient alternative over conventional DPSK modem. Real-time verification is performed using Kintex-7 FPGA board. The performance of the proposed modem has been compared with a normal DPSK modem implemented in software defined radio kit using Xilinx block and Spartan-6 FPGA.

Keywords:

• CORDIC
• DPSK
• FPGA
• RTL schematic
• SDR

Additional information

Funding

Subir Kumar Sarkar thankfully acknowledges the financial support for this research work obtained from UPE II Programme with Ref. No: R-11/43/2013.

Notes on contributors

Joyashree Bag

Joyashree Bag was born in Kolkata, West Bengal, and received M Tech degree in VLSI design and microelectronics engineering from Jadavpur University (JU). She is with the Department of Electronics and Communication Engineering, Meghnad Saha Institute of Technology, Kolkata, India, and is currently pursuing her research leading to PhD at Jadavpur University as a research fellow. Her research field is VLSI design and development of RFID technology based systems/ASICs and hardware realization upto RTL schematic level using VHDL code and system level implementation using FPGA.

E-mail: [email protected]

Subhashis Roy

Subhashis Roy received M Tech in VLSI design and microelectronics technology from JU in the year 2013. He is currently working as junior research fellow for CSIR sponsored project at ETCE Department, JU, under supervision of Prof. (Dr) Subir Kumar Sarkar. His research field is FPGA and RFID based system design and implementation.

E-mail: [email protected]

P. K. Dutta

Mr Pranab Kishore Dutta is an assistant professor in the Department of Electronics and Communication Engineering, in North Eastern Regional Institute of Science & Technology, Arunachal Pradesh. Presently he is pursuing his PhD in engineering from JU under AICTE QIP fellowship programme. His area of interest is VLSI circuits and nano devices.

E-mail: [email protected]

Subir Kumar Sarkar

Dr Subir Kumar Sarkar is with the Department of Electronics and Telecommunication Engineering as professor and head of the department. He has numerous research papers in archival journals and peer reviewed conferences. Twenty-six students have been awarded PhD degree under his guidance so far. As a principal investigator he has successfully completed six sponsored R&D projects. He is a senior member of IEEE. His research area includes RFID applications and system realization, ad hoc and sensor networks, digital watermarking and data hiding, electron device simulation, and low power VLSI circuits.

E-mail: [email protected]