A Low-Jitter Fast-Locking Multi-phase Clock for High Resolution CCD Processor

ABSTRACT

A multi-phase clock circuit for a 14 bit 80 MHz charge-coupled device (CCD) signal processor is designed based on the Delay-Locked Loop (DLL) structure. To accelerate the DLL locking time, a new fast locking controller circuit is proposed in this paper. Besides, a low jitter delay cell circuit is used to reduce the influence of the jitter generated by multiple phase clock generating circuit on the performance of correlated double sampling (CDS) and A/D conversion in the high resolution CCD signal processor. A clock signal with adjustable phase for the CCD signal processor can be obtained by changing the value of the edge selected register. The proposed clock circuit implemented and simulated with SMIC 0.18 μm 3.3 V 1P6M mixed CMOS process and the area of layout is 1000 × 350 μm. Under the condition of TT/3.3V/27 °C, the simulation results with the input clock frequency of 80 MHz show that the DLL locking time is 1.3 μs. Besides, the peak-to-peak jitter is 1.09 ps and the RMS jitter is 182 fs.

Keywords:

• Multi-phase
• Clock circuit
• Delay locked loop
• Fast lock
• CCD signal processor
• Correlated double sampling
• Edge selected register

Funding

This work was supported by the National Natural Science Foundation of China [grant number 61376033], [grant number 61234002], [grant number 61322405], [grant number 61306044]; the National High-tech Program of China [grant number 2012AA012302], [grant number 2013AA014103].

Additional information

Notes on contributors

Lianxi Liu

Lianxi Liu received the MS and PhD degrees in microelectronics from Xidian University, Xi'an, P.R. China, in 2004 and 2006, respectively. He is currently an associate professor with the School of Microelectronics, Xidian University, Xi'an, P.R. China. His research interests include high speed CMOS data converters, mixed-signal integrated circuits design, and low voltage low power analog circuits design.

Email: [email protected]

Ning Ma

Ning Ma received the BS degree in microelectronics at Xidian University, Xi'an, P.R. China. She is now pursuing the MS degree at the School of Microelectronics, Xidian University. Her research interests include deep submicron SoC design and mixed-signal integrated circuits design.

Email: [email protected]

Yang Zhao

Yang Zhao received the B.S and M.S degree in microelectronics at Xidian University, Xi'an, P.R. China. His research interests include high speed CMOS data converters and mixed-signal integrated circuits design.

Email: [email protected]

Wei Guo

Wei Guo received the BS and MS degree in microelectronics at Xidian University, Xi'an, P.R. China. He is now pursuing the PhD degree at the School of Microelectronics, Xidian University. His research interests include high speed CMOS data converters and mixed-signal integrated circuits design.

Email: [email protected]

Shubin Liu

Shubin Liu received the BS and MS degree in microelectronics at Xidian University, Xi'an, P.R. China. He is now pursuing the PhD degree at the school of microelectronics, Xidian University. His research interests include high speed CMOS data converters and mixed-signal integrated circuits design.

Email: [email protected]

Zhangming Zhu

Zhangming Zhu received the MS and PhD degrees in microelectronics from Xidian University, Xi'an, P.R. China, in 2001 and 2004, respectively. He is currently a professor of the School of Microelectronics, Xidian University, Xi'an, P.R. China. His research interests include electronic design automation, mixed-signal integrated circuits design, and 3D-ICs.

Emai: [email protected]