Gate Tunnelling Current Model for Nanoscale MOSFETs with Varying Surface Potential

ABSTRACT

At nanoscale, the channel of metal oxide semiconductor field effect transistors (MOSFETs) acts like a potential well within which electron energy levels are quantized and a nonzero wavefunction is obtained at the oxide–semiconductor interface. As a result the gate tunnelling current has emerged a significant constraint in respect of scaling of ultrathin gate oxides. We have developed an analytical model considering varying surface potential with applied voltage for evaluating gate tunnelling current through thin dielectrics in nanoscale MOSFETs. The electron wavefunction has been calculated by treating the band profile in the channel as a triangular potential well. The tunnelling probability through the gate oxide has been evaluated using Jeffreys–Wentzel–Kramers–Brillouin approximation method. The tunnelling current density is estimated from the evaluated interface wavefunction along with the tunnelling probability. The results from the present model compare well with the published Mondal–Dutta model and the experimental data. The novelty of the present model lies in its simplicity and its analyticity requiring much less computational efforts for its implementation.

Keywords:

• gate leakage
• MOSFET
• potential well
• semiconductor device modelling
• tunnelling
• wavefunction

Acknowledgements

We acknowledge the facility and support provided by the Department of Electronics and Communication Engineering, Thapar University, Patiala, India, and the Department of Electronic Science, Kurukshetra University, Kurukshetra, India.

Disclosure statement

No potential conflict of interest was reported by the authors.

Additional information

Notes on contributors

Madhu Kushwaha

Madhu Kushwaha was born in Julich, Germany, in 1979. She received the BTech degree in electronics and communication in 2002 from M. J. P. Rohilkhand University, Bareilly, Uttar Pradesh, India, and MTech degree in microelectronics in 2008 from Panjab University, Chandigarh, India. She is currently pursuing the PhD degree at the Department of Electronics and Communication Engineering, Thapar University, Patiala, Punjab, India. Her current research interest is modelling of single and double gate MOSFETs.

E-mail: [email protected]

B. Prasad

B. Prasad received the BSc degree in 1980 from Kerala University, Kerala, India, and the MSc degree in physics in 1982, MPhil in 1992, and PhD in 2002, all from Kurukshetra University, Kurukshetra, Haryana, India. His thesis was on Monte Carlo simulation techniques for electron transport in silicon. He is professor at Kurukshetra University, Kurukshetra, India. Since 1982, he has been involved in design and fabrication of semiconductor devices, development and fabrication of glass laser oscillator–amplifier system, which could be used for laser annealing of ion implanted silicon. His current research involves device modelling especially for submicron and nanoscale devices, study of oxy-nitride film as a possible gate material in submicron MOSFETs and reconfigurable hardware.

E-mail: [email protected]

A. K. Chatterjee

A. K. Chatterjee received the MSc degree in electronics 1971 from Jadavpur University, Kolkata, India, MTech degree in 1977 from Brunel University, UK, and PhD in 1986 from University of Jabalpur, India. His thesis was on analytical study of the optical properties of CdS thin films under low temperature annealing. His research area involves semiconductor device physics, silicon carbide power semiconductor devices, microelectronics, and ICs. His current research includes simulation and modelling of semiconductor devices. He has authored a number of papers in reputed journals as well as many conference papers. He is professor at Thapar University, Patiala, Punjab, India.

E-mail: [email protected]