Multilevel Codes with Hierarchical Set Partitioning

ABSTRACT

Two novel multilevel coding schemes are proposed. The first multilevel coding structure is based on set partitioning of an inner multilevel code and the second one is a modified design in which the partition chain is constructed from a multilevel code with interblock memory. Simulation results show that the proposed schemes can achieve good error performance with low decoding complexity. As a result, the proposed coding schemes provide more design flexibility under various communication conditions.

KEYWORDS:

• Interblock memory
• multilevel codes
• set partitioning

Disclosure statement

No potential conflict of interest was reported by the authors.

Additional information

Notes on contributors

Shang-Chih Ma

Shang-Chih Ma was born in Keelung, Taiwan, R.O.C., on 16 December 1966. He received the BS and PhD degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 1988 and 1994, respectively. He was a design engineer at the Department of Digital Video Broadcast System, Computer and Communication Research Laboratories, Industrial Technology Research Institute, Hsinchu, Taiwan, R.O.C., from 1994 to 2002. He is currently with the Department of Electrical Engineering, National Taipei University of Technology, Taiwan, R.O.C., as an associate professor. His research interests include digital communication systems and coding theory.

Email: [email protected]

Po-Yueh Chen

Po-Yueh Chen received the BS, MS, and PhD degrees in electrical engineering from National Taiwan University in 1988, National Chiao Tung University in 1990, and the University of Maryland at College Park in 1997, respectively. Currently, he is a faculty member in the Department of Computer Science and Information Engineering, National Changhua University of Education, Changhua, Taiwan. His research interests include image processing, FPGA implementations, VLSI architecture design, and digital IC design.

E-mail: [email protected]