Reliability Analysis of P⁺ Pickup on Anti-ESD Performance in Four CMOS Low-Voltage Technology Nodes

ABSTRACT

N-channel metal-oxide semiconductor field-effect transistor (MOSFET) devices in I/O ESD protection circuits are often drawn in the parallel multi-finger construction. However, a non-uniform turned-on characteristic always occurs with this type of construction; i.e. the resulting sub-MOSFETs cannot be turned on at the same time. The ESD high-current will thus be conducted through a few turned-on MOSFETs, seriously impacting the ESD reliability and capability. On the source-side, the P⁺ pickup layout placement influence on an nMOSFET ESD capability of input/output pads for power-management popular 0.6- to 0.18-μm BCD (bipolar–complementary metal oxide semiconductor–diffusion metal oxide semiconductor) CMOS (complementary metal oxide semiconductor) technologies is investigated in this paper. However, the I_t2 decreasing percentage in an even- and full-adding type of P⁺ pickup stripe in the source end, as compared with that of a corresponding NonePickup Ref. type, is actually disadvantageous to the ESD immunity. The secondary breakdown current (I_t2) decreasing percentages have a range of 2.43%–63.31% for the four process nodes. This is very serious for the three technology nodes especially in the ultra-deep submicron 0.18-μm technology. On the contrary, the 0.35-μm technology is a critical process node. Furthermore, the figure of merit (FOM) for a device's ESD performance in a multi-finger type MOSFET can be used to well characterize and predict the device's I_t2 behaviour using an empirical methodology proposed in this work.

KEYWORDS:

• Bipolar-CMOS-DMOS (BCD)
• Electrostatic discharge (ESD)
• Gate-grounded n-channel MOSFET (GGnMOS)
• Latch-up (LU)
• Pickup
• Secondary Breakdown Current (I_t2)
• transmission-line-pulse (TLP)

ACKNOWLEDGMENTS

In this work, authors would like to thank the National Chip Implementation Center in Taiwan for providing the process information and fabrication platform. And, authors would like to acknowledge the financial support of the Ministry of Science & Technology of Taiwan, through grant number [MOST 103-2221-E-239-014].

DISCLOSURE STATEMENT

No potential conflict of interest was reported by the authors.

Additional information

Funding

Ministry of Science & Technology of Taiwan [grant number MOST 103-2221-E-239-014].

Notes on contributors

Shen-Li Chen

Shen-Li Chen received PhD degree from National Tsing-Hua University, Taiwan, in 1992. He joined the ERSO, ITRI, Taiwan in 1987, and worked at the R&D department responsible for reliability analysis in submicron circuits. After then, he also acted a director of AX and CG Electronics Corporation in R&D division, focused on I/O ESD/Latch-up cells design especially used in HV processes and the DC-DC analog circuit design.In 2001, he joined the Department of Electronic Engineering of National United University, Taiwan, as an associate professor. In 2003, he was the chairman of Department of Electronic Engineering of National United University, Taiwan. In 2013, he also was an adjunct professor of Software and Microelectronics School at Wuxi of Peking University, China. Recently, he continued to pursue his research interests in the modelling and characteristic of HV power devices, and high ESD/LU immunity designs in VLSI and power electronics.

E-mail: [email protected]

Min-Hua Lee

Min-Hua Lee received master degree from the Department of Electronic Engineering of National United University, Taiwan, in July 2013. His current projects focus on the anti-ESD protection design and cells library establishment in the Himax Technologies, Inc., Taiwan.

E-mail: [email protected]