A Precise Design for Testing High-Speed Embedded Memory using a BIST Circuit

ABSTRACT

Built-in self-test (BIST) mechanism has been a very important approach for testing embedded memory's function and performance. In this paper, a high-speed BIST design for embedded static random access memory (SRAM) and one-port register file (RF) IPs testing was presented. With the purpose of achieving high-speed requirement, the pipe-line strategy is adopted in BIST circuit. Four SRAM instances and four one-port RF instances with the BIST circuit are integrated in a test chip. And the test chip has been fabricated in 28 nm low-leakage logical process. The final silicon data indicated that the proposed implementation is efficient and reliable for memory testing. Furthermore, the test result also show that the yield of memory instances with BIST circuits in the test chip reached up to nearly 100%.

KEYWORDS:

• BIST
• Memory testing
• One-port register file
• Pipe-Line
• SRAM
• 28 nm

ACKNOWLEDGMENTS

This work was supported by National Natural Science Foundation of China, [Grant Numbers No.61272105, and No.61076102.] This work was also supported by the Opening Project of Key Laboratory of Microelectronic Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences.

DISCLOSURE STATEMENT

No potential conflict of interest was reported by the authors.

Additional information

Funding

This work was supported by National Natural Science Foundation of China, [Grant Numbers No.61272105, and No.61076102.]

Notes on contributors

Lijun Zhang

Lijun Zhang received the BS degree from the Huazhong University of Science and Technology, Wuhan, China, in 1993 and the MS and PhD degrees from the Institute of Microelectronics of Chinese Academy of Sciences, Beijing, China, in 1997 and 2000, respectively. He is currently working in the School of Urban Rail Transportation, Soochow University, Suzhou, China, and doing works on SRAM stability and low power SRAM design in sub-65nm CMOS. His interests are VLSI design, embedded memory design and testing for SoC, and networking IC design.

E-mail: [email protected]

Ziou Wang

Ziou Wang received the BS degree from the Peking University of Microelectronics, Beijing, China, in 1996. He received the PhD degree from Peking University in 2001. He joined the School of Electronic and Information Engineering of Soochow University in 2004. His research interests are nanometer semiconductor device and storage systems.

E-mail: [email protected]

Youzhong Li

Youzhong Li is research student in the School of Urban Rail Transportation in Soochow University, Suzhou, China. Currently, he is doing research on semiconductor memory including SRAM, flash, and so on. His research interests include semiconductor memory in advance technology.

E-mail: [email protected]

Lingfeng Mao

LingFeng Mao received the PhD degree in microelectronics and solid state electronics from Peking University, Beijing, P.R. China, in 2001. He is a professor in the School of Electronics and Information Engineering, Soochow University, P.R. China. His research activities include modeling and characterization of microelectronic devices and circuit, the fabrication and modeling of integrated optic devices and microwave devices.

E-mail: [email protected]