Transmission Gate as Buffer for Carbon-Nanotube-Based VLSI Interconnects

ABSTRACT

In this paper, we propose transmission gates (TGs) as buffers/repeaters for carbon nanotube (CNT)-based VLSI interconnects. Various performance metrics of the TG buffer, viz. propagation delay, crosstalk-induced delay, power dissipation, and power-delay product under super-threshold and sub-threshold conditions are analysed. Performance analysis of TG buffers with CMOS inverter buffers at various interconnect lengths and buffer insertion intervals is done. We have also analysed the performance of Single-wall carbon nanotube (SWCNT) bundle and three different configurations of mixed CNT bundles. By comparing the power-delay product of both the buffers, it is found that TG buffers are more suitable for applications in CNT-based integrated circuits.

KEYWORDS:

• Transmission gates
• Inverter
• Buffer
• Delay
• Power dissipation
• CNT interconnects
• Power-delay product

DISCLOSURE STATEMENT

No potential conflict of interest was reported by the authors.

Additional information

Notes on contributors

A. Karthikeyan

A. Karthikeyan received his BE (EEE) degree from Madras University in 2002 and his ME (Applied Electronics) degree from Anna University in 2005. He is currently pursuing his PhD degree from School of Electrical Engineering, VIT University, where he is also working as an assistant professor since 2010. His areas of interest include VLSI interconnects and circuits.

E-mail: [email protected]

P.S. Mallick

P. S. Mallick (SM'10) is a senior professor and Former Dean of the School of Electrical Engineering, VIT University, India. He was the technical head of IAAB Electronics a Swedish Industry in Bangladesh. He led various research teams and developed online laboratory in microelectronics, Monte Carlo simulator of compound semiconductors, nanostructured MIM capacitor, and low-cost electric fencers. He is currently a professor of electronics engineering and the director of Office of the Ranking and Accreditation, VIT University. He has authored 82 research papers in different journals and conferences of international repute. His recent interest includes advancement of technical education through innovations. He is the past Chapter Chair and a present Chapter Adviser of the IEEE-EDS VIT of Region 10 Asia-Pacific. He was an enlisted technical innovator of India in 2007. He has published a book on Matlab and Simulink and IET, UK, has published his book chapter on MIM Capacitor in June 2016. At present, Dr Mallick is finding new materials and technology for future nano scale electronics.

E-mail: [email protected]