A Compact Electrical Modelling for Top-Gated Doped Graphene Field-Effect Transistor

ABSTRACT

In this paper, we have developed an inclusive model for top-gated doped graphene field-effect transistor (GFET). The proposed model is concise and accurate for calculations of the electrical parameters that are used in digital circuit design. The doping in single layer graphene sheet is one of the ways to create a bandgap as well as to introduce the threshold voltage (V _TH) concept in GFET. Further, the modelled expressions are used for estimation of quantum capacitance (C_q ), which is used for the modelling of drain current (I_D ), small-signal transconductance gain (g_m), output resistance (r_o ), and figures of merit such as intrinsic voltage gain (A_V ), transconductance efficiency (g_m/I_D), and cut-off frequency (f_T).

KEYWORDS:

• Advance channel materials
• Device modeling
• Nanoelectronics
• Nanotechnology

DISCLOSURE STATEMENT

No potential conflict of interest was reported by the authors.

Additional information

Notes on contributors

Abhishek Kumar Upadhyay

Abhishek Kumar Upadhyay received the MSc degree in Electronics from the University of Gorakhpur, UP, India in 2010 and MTech degree in ECE from UPTU, India, in 2012.

He is currently working towards the PhD degree at the Indian Institute of Technology, Indore. His current research interests include modelling and simulation of circuit design, nanotechnology, solid-state devices, and semiconductor devices. Recently, his research is focused on modelling and simulation of 2D channel materials for MOSFET used in digital and analogue/RF circuits.

E-mail: [email protected]

Nitesh Chauhan

Nitesh Chauhan is currently a final year student of Electrical Engineering undergraduate course at the Indian Institute of Technology Indore, India.

His current research interest includes 2D nanoelectronic material especially graphene and novel devices based on these materials. He is also interested in signal and image processing, particularly in fingerprint biometric.

E-mail: [email protected]

S. K. Vishvakarma

S. K. Vishvakarma received the Bachelor of Science (BSc) degree in Electronics from the University of Gorakhpur, UP, India, Master of Science (MSc) degree in Electronics from D.A.V.V. Indore, MP, India, and Master of Technology (M Tech) degree in Microelectronics from the University of Chandigarh, Punjab, India in 1999, 2001, and 2003, respectively. At present, he is with the Electrical Engineering Discipline, School of Engineering, Indian Institute of Technology (IIT), Indore, India, as an assistant professor.

E-mail: [email protected]