High-Q and Wide-Bandwidth Capacitor Multiplier Optimized by NSGA-II

ABSTRACT

Power management applications require the use of large value on-chip capacitors that can be implemented by active circuits scaling the value of a physical capacitor. However, a good capacitor scaler must provide the best frequency response and high quality factor (Q), accompanied by the minimum power consumption and silicon area. In this manner, a new C-multiplier topology is introduced herein, designed by using 180 nm CMOS integrated circuit technology, and optimized by applying the Non-Dominated Sorting Genetic Algorithm II (NSGA-II). Spice is linked to NSGA-II to evaluate electrical characteristics, while Q and the quiescent current (I_Q ) were selected as the optimization objectives. The feasible solutions are given in a Pareto front, from which we selected the one providing the best frequency response with a multiplication factor (MF) = 1001 and Q = 278, and consuming 93 μA of static current. Finally, we show that the optimized C-multiplier achieves class AB performance and fits the passive model of a real capacitor very accurately in a wide range of frequencies. 

KEYWORDS:

• Capacitor multiplier
• Dynamic class AB current mirror
• MOSFET
• NSGA-II

ACKNOWLEDGMENT

The authors would like to thank CONACYT-Mexico for the funding project [grant number 237991].

DISCLOSURE STATEMENT

No potential conflict of interest was reported by the authors.

Additional information

Funding

Consejo Nacional de Ciencia y Tecnología, Mexico [grant number 237991].

Notes on contributors

Jesus López-Arredondo

Jesus Lopez-Arredondo received a BSc degree from Instituto Tecnológico de Mexicali, Baja California, México. He then received the MSc degree at Instituto Nacional de Astrofísica, Óptica y Electrónica (INAOE), México, in 2015. His research interests include modelling and simulation of circuits and systems, design and applications of integrated circuits, and multi-objective evolutionary algorithms.

E-mail: [email protected]

Esteban Tlelo-Cuautle

Esteban Tlelo-Cuautle received a BSc degree from Instituto Tecnológico de Puebla (ITP), México in 1993. He then received both MSc and PhD degrees from Instituto Nacional de Astrofísica, Óptica y Electrónica (INAOE), México, in 1995 and 2000, respectively. He has published 13 books and more than 250 works in book chapters, journals, and conferences. He is an associate editor of IEEE Transactions on Circuits and Systems I: Regular Papers, and Integration - the VLSI Journal. His research interests include modelling and simulation of circuits and systems, design and applications of chaotic oscillators, symbolic analysis, multi-objective evolutionary algorithms, and analogue/radio frequency (RF) and mixed-signal design automation tools.

Corresponding author E-mail: [email protected]

Luis Gerardo de la Fraga

Luis Gerardo de la Fraga received the BS degree in electrical engineering from Instituto Tecnológico de Veracruz, Veracruz, México in 1992. He then received the MSc degree from Instituto Nacional de Astrofísica, Óptica y Electrónica (INAOE), Puebla, México, in 1994; and the PhD degree from Autonomous University of Madrid, Spain, in 1998. Since 2000, he is in the computer science department at the Center of Research and Advanced Studies (Cinvestav), in Mexico City. His research areas include computer vision, optimization, and network security. He is very enthusiastic of open software and GNU/Linux systems. Dr de la Fraga has published 1 book and more than 60 articles in journals and international conferences. He is a member of ACM and IEEE societies since 2005.

E-mail: [email protected]