CAD Layout Analysis for Defect Inspection in Semiconductor Fabrication

ABSTRACT

We have been witnessing the continuous size reduction in consumer electronics devices with longer battery life. The Application Specific Integrated Circuits allow for integration of multiple electronics devices on the same dice. At the same time optimizing the transistor and device area lowers power consumption. It is a big challenge to develop such semiconductor processes and also to develop methodologies to monitor the process during semiconductor fabrication. After every major fabrication process, the wafer undergoes an inspection to detect any abnormality that may cause chip failure down the line. An optical inspection using Ultra Violet or Deep Ultra Violet light is designed to find the physical defects that might be “visible” on the wafer. In order to find electrical connection failure during fabrication, a separate approach of electron beam inspection is designed for monitoring metallization processes. In this study, we have used Computer Aided Design layout analysis to guide the defect inspection for both optical and electron beam wafer inspections. The goal was to increase the chances of finding critical defects as well as to reduce the cycle time for the inspection and defect characterization. The proposed approach has been compared with the existing baseline inspection results on the same wafer.

KEYWORDS:

• ASIC
• Design optimization
• DFM
• IC manufacturing
• Pattern defects
• Wafer inspection

Additional information

Notes on contributors

Abhishek Vikram

Abhishek Vikram FIETE, SMIEEE has received Bachelor of Technology degree in electronics engineering with honours in 2001 from the autonomous Kamla Nehru Institute of Technology Sultanpur, India and a PhD in electrical engineering from Motilal Nehru National Institute of Technology, Allahabad, India. He has been working in different engineering roles in the chip design and manufacturing industry for over 18 years. His research interests are in applications of design knowledge in chip manufacturing to improve yield. He has a number of patents and publications in International Journals and Conferences in this field. E-mail: [email protected]

Vineeta Agarwal

Vineeta Agarwal FIE, SMIEEE, has graduated from Allahabad University, India, in 1980, and received master’s degree in Electrical Engineering in 1984, from the same university. She joined as lecturer in 1982 in Electrical Engineering Department in MNR Engineering College and since then she has been teaching in the same college. While teaching, she did her PhD in power electronics in 1993. At present, she is Professor of Electrical Engineering at MNNIT, Allahabad. She has taught numerous courses in Electrical and Electronics. Her research interests are in single phase to three-phase conversion, resonant converters, AC drives and emerging topics. She has a number of publications in Journals and Conferences in this field. She has attended both National and International Conferences and presented papers there.

Anshul Agarwal

Anshul Agarwal graduated from the Uttar Pradesh Technical University, Lucknow, India, with BTech degree in electrical and electronics engineering in 2007 and completed his MTech (Gold Medalist) in power electronics and ASIC design at MNNIT, Allahabad, in July 2009. He is working as Assistant Professor in Electrical Engineering Department, NIT Delhi, India. His research interests include power electronic devices, converters, inverters and AC to AC converter, application of power electronics to renewable energy. E-mail: [email protected]