Novel Subthreshold Modelling of Advanced On-Chip Graphene Interconnect Using Numerical Method Analysis

ABSTRACT

In VLSI integrated circuits, devices and interconnects are the steady pillars for designing and realization of the entire system. Demand for ultra-low power requirements has become very essential in today’s modern portable and miniaturized electronic gadgets. The subthreshold modelling and its utility for miniaturized gadgets and low power applications have increased tremendously in recent days. Operating devices and interconnects in the subthreshold region profoundly enhance the performance of the system. In this paper, contemporary subthreshold modelling has been energetically taken. The novel modelling of subthreshold for device and on-chip interconnects has been first time presented using the numerical method based finite-difference time-domain (FDTD) technique. The advanced graphene on-chip interconnects have been considered for the performance analysis. The technology node considered is 22 nm. It is analysed that graphene-based MLGNR interconnects possess better performance over copper interconnects. It is also seen that subthreshold region of operation leads to significantly lower power dissipation than in linear region. Power saving with the subthreshold region of operation in case of conventional copper and advanced graphene interconnects is nearly 22% and 26% respectively. The veracious proposed FDTD modelling for the subthreshold region is highly accurate with respect to SPICE simulation results. The average percentage error for transient simulation is less than 2%.

KEYWORDS:

• FDTD
• Integrated circuit
• Interconnect
• Nanotechnology
• Numerical method
• Propagation delay
• VLSI

Additional information

Notes on contributors

Nikita R. Patel

Nikita R. Patel received BE degree in electronics and communication engineering from Govt. Engineering College, Patan, Gujarat, India, in 2013, and currently pursuing MTech degree in VLSI Design from Dhirubhai Ambani Institute of Information and Communication Technology, Gandhinagar, Gujarat, India. Her research interests include VLSI interconnects and next-generation graphene-based interconnects.

Yash Agrawal

Yash Agrawal received his MTech and PhD degrees in VLSI design automation and techniques from National Institute of Technology, Hamirpur, Himachal Pradesh, India, in 2012 and 2016, respectively. Presently, he is working as Faculty at DA-IICT Gandhinagar, Gujarat. His current research interests include nanotechnology, modelling and analysis of nano devices and interconnects. He achieved university rank during his bachelor’s degree. He achieved third place in All India Mentor Graphics design contest held at Bangalore, India, in 2011. He has been the chairman and awarded with best forum member of IETE Students’ Forum at KITS Ramtek, Nagpur Division during 2008–2009. He has also been awarded first rank in various national and inter-college level paper presentations. He is member of IEEE. Email: [email protected]

Rutu Parekh

Rutu Parekh received her ME in electrical engineering from Concordia University, Canada, PhD in electrical engineering (nanoelectronics) from Université de Sherbrooke, Canada, and Postdoctoral fellow at Centre of Excellence in Nanoelectronics, IIT Bombay, in 2015. She is currently working as a Faculty at DA-IICT, India. Her research interest includes developing models, co-design methodology and co-simulation of hybrid circuits of emerging nanoelectronic devices with CMOS technology, low voltage low power circuits, embedded systems and IOE. She is member of IEEE. Email: [email protected]