A Low-Power VLSI Implementation of RFIR Filter Design using Radix-2 Algorithm with LCSLA

ABSTRACT

The multimedia applications and mobile communication systems require an efficient reconfigurable finite impulse response (RFIR) filter designs for achieving low area, power, cost, and high speed of system operation. In this paper, an efficient RFIR filter is designed based on the Radix-2 algorithm and Look-up-table Carry Select Adder (Radix 2 – LCSLA). Generally, the RFIR filter is controlled by multiplier and adder, which improves the performances of the filter. Hence, this research work is mostly concentrated on the multiplier and adder design. Here, the radix-2 algorithm is used instead of normal multiplier for multiplication operation in the RFIR filter design. Additionally, CSLA and LCSLA approaches used in the Radix-2 structure for adding partial products. The LCSLA has achieved better performance compared to the normal CSLA approaches. In this paper, both the Radix-2 algorithm and LCSLA approach improved the performances of the proposed RFIR filter design. The proposed RFIR filter design was implemented in the Xilinx and Cadence RTL compiler by using the Verilog code. The RFIR-Radix 2-LCSLA filter design was verified in the Modelsim by utilizing the Verilog code. The experimental result showed that the RFIR-Radix 2-LCSLA methodology has improved the performance of ASIC and FPGA in the RFIR filter design up to 5–15% compared to the existing filter architecture: DA-RFIR and LC-CBA-RFIR methods.

KEYWORDS:

• Carry select adder
• Modelsim
• Reconfigurable finite impulse response
• Radix-2 algorithm
• Verilog code

Additional information

Notes on contributors

Kasarla Satish Reddy

Kasarla Satish Reddy received his Bachelor of Technology (electronics and communication engineering) from JNT University, Hyderabad in 2001. He received his Master of Science (VLSI design) from University of Texas Dallas, the USA in 2004 and his second Master of Science (optical science and engineering) from University of New Mexico Albuquerque, the USA in 2009. He is currently pursuing his Doctor of Philosophy degree from Visvesvaraya Technological University, Belagavi in the field of VLSI design. He has to his credit 14 National and International Research publications with 46 citations. He has 8 years of teaching and 7 years of industrial experience. His research interests include advance filter designs using novel VLSI design architectures and advanced microstrip antenna designs for wireless applications.

Hosahally Narayangowda Suresh

Hosahally Narayangowda Suresh received his BE (E&C) from P E S College of Engineering, Mandya in 1989 and completed his MTech (bio medical instrumentation) in 1996, from SJCE Mysore affiliated to University of Mysore. He obtained his PhD (ECE) from Anna University of Technology. Presently, he is actively involved in the area of teaching and research and obtained 30 years of experience in teaching. He has worked in various capacities at affiliated University Engineering Colleges. For Visvesvaraya Technological University and Bangalore University, he worked as a Chairman for Board of Examiners, and Member of Board of Studies, etc. At present he is working as Professor and coordinator for PG Studies and Research at Bangalore Institute of Technology, Bangalore, affiliated to Visvesvaraya Technological University. He has good exposure in the field of signal processing, wavelet transforms, neural networks, pattern recognition, bio medical signal processing, networking and adaptive neural network systems. He has published more than 75 research papers in the international journals and presented contributed research papers in international and national conferences. He is guiding more than 15 PhD Students and more than 100 MTech Scholars. He is a member of IEEE, Bio Medical Society of India, ISTE, IMAPS & Fellow member of IETE. E-mail: [email protected]