Fin Angle Variation Oriented Threshold Voltage Model for a FDSOI FinFET

Abstract

To support the current level of integration beyond 22 nm, the FinFET architecture is introduced with the expectation of greater levels of device matching. An additional mechanism, arising from charges present at points of disturbance in the silicon lattice in tapering and wavering fins is shown to contribute significantly to transistor mismatch. As the fin is being tapered, quantum mechanical effects come into scene, which contribute to threshold voltage mismatch in the device. This atomic level jogs arise along the taper length of the device can introduce a significant amount of unpassivated charges along the fin. We show that including this mechanism can improve the quantitative understanding of mismatch in FinFETs. For this purpose, an ideal FDSOI FinFET with various fin angles are considered. The existing models are not in agreement with these effects to understand the device better. An analytical model is necessary to relate this mismatch due to differences in threshold voltages with fin angle variation which helps to analyse the influence of the FinFET sidewall inclination angle on the threshold voltage. Threshold voltage and intrinsic trap variations for various fin angles and surface charge densities are measured for analytical study. An optimized threshold voltage equation including the effects of quantum mechanism and channel reduction is developed. The simulations are done through a 3D TCAD simulator Atlas Silvaco and validation of model has done in MATLAB tool.

KEYWORDS:

• Atlas simulator
• FDSOI FinFET
• Fin angle
• Mismatch
• TCAD simulation
• Threshold voltage model
• Trapezoidal

Additional information

Notes on contributors

T. E. Ayoob Khan

T E Ayoob Khan received his bachelors degree, BTech (Electronics and Communication Engineering) from Mahatma Gandhi University, Kottayam, India in 1995 and masters degree, ME (Applied Electronics) from PSG College of Technology, Coimbatore, India in 2008. He has 21 years of teaching experience. He is currently with College of Engineering, Chengannur, Kerala, India as associate professor in Electronics Engineering Department. He is a member of IEEE, IEEE Solid State Circuit Society, IEEE Electron Devices Society and ISTE. His areas of interests are VLSI design and MOSFET devices.

S. Salini

Salini S received her bachelor's degree, BTech (Electronics and Communication Engineering) from Mahatma Gandhi University, Kottayam, India in 2014 and is doing her master's degree, MTech (VLSI and Embedded Systems) in College of Engineering Chengannur, Kerala, India. She was a member of IEEE and IEEE Solid State Circuit Society. Her areas of interests are VLSI devices and Digital VLSI design.Email: [email protected]

Geethu Maria Abraham

Geethu Maria Abraham received her bachelor's degree, BTech (Electronics and Communication Engineering) from Cochin University of Science and Technology, Kochi India in 2013 and is doing her master's degree, MTech (VLSI and Embedded Systems) in College of Engineering Chengannur, Kerala, India. She was a member of IEEE and IEEE Solid State Circuit Society. Her areas of interests are VLSI devices and digital VLSI design.Email: [email protected]

T. A. Shahul Hameed

Shahul Hameed T A received his bachelor's degree, BTech (Electronics and Communication Engineering) from University of Kerala, India, MTech (Microelectronics and VLSI Design) from IIT Kharagpur, India and PhD (Electronics and Communication Engineering) from University of Kerala, India. He has 20 years of teaching experience and 8 years of industrial experience. He is currently with TKM College of Engineering, Kollam, Kerala, India a professor in Electronics and Communication Engineering Department. He has authored more than twenty international journal and conference papers. His areas of interests are organic devices, quantum devices and device modelling.Email: [email protected]