Analysis of Temperature-Dependent Crosstalk for Graphene Nanoribbon and Copper Interconnects

Abstract

In this article, we propose a temperature-based crosstalk analysis model for rough edge graphene nanoribbon (GNR) and Cu interconnect. Temperature-dependent crosstalk delay and noise analysis for 16 nm technology node (ITRS-2011) is performed for three different chip-operating temperatures are −40°C (233 K), i.e. low temperature, 27°C (300 K), i.e. room temperature, and 105°C (378 K), i.e. high temperature. Our analysis shows that, first by increasing the temperature from 233 to 378 K and also by increasing interconnect length from 10 to 100 µm, the GNR shows less amount of crosstalk-induced delay compared with Cu interconnect and crosstalk noise increase slightly which indicates the performance degradation and reliability issues, second the GNR-based interconnect produce (%) variation in delay due to crosstalk and crosstalk noise is lesser than Cu interconnect when interconnect length increase from 10 to 100 µm by increasing temperature. Hence, GNR interconnect is much more thermally viable as compared with traditional Cu-based interconnect and it is very much useful for nano-scale interconnect modeling.

KEYWORDS:

• Crosstalk
• Graphene nanoribbon (GNR)
• Interconnect
• Mean free path (MFP)
• Temperature

Additional information

Funding

This work was supported by University Grants Commission [grant number 2013-18485].

Notes on contributors

Sandip Bhattacharya

Sandip Bhattacharya was born in Pandaveswar, Burdwan, West Bengal, India, on 21 July 1983. He received the BE degree in electronics and communication engineering (ECE) from University Institute of Technology (UIT), University of Burdwan (BU), India in 2006, MTech degree in electronics and communication engineering (ECE) (Embedded Systems) from West Bengal University of Technology, India in 2011 and PhD degree in VLSI from School of VLSI Technology, Indian Institute of Engineering Science and Technology (IIEST), Shibpur, Howrah, India in 2017. He is presently working as a post-doctoral researcher in HiSIM Research Center, Hiroshima University, Japan. He has published more than 37 research articles in archival journals and refereed conference proceedings. He received IETE J.C Bose Memorial Award for the best paper in 2018. He is serving as a reviewer in IET Micro-nano Letters, IET Circuit Device and Systems, Journal of Computational Electronics (JCEL) Springer, IEEE Access etc. His research interests include VLSI design, interconnect modeling and artificial intelligence based circuit design for robotics application. E-mail: [email protected]

Debaprasad Das

Debaprasad Das (M’12) was born in Haria, Purba Medinipur, West Bengal, India, on 10 May 1975. He received the BSc (Hons.) degree in physics from Vidyasagar University, Midnapore, India, in 1995, the BTech degree in radiophysics and electronics from University of Calcutta, Kolkata, India in 1998, the ME degree in electronics and telecommunication engineering from the Jadavpur University, Kolkata, in 2006 and PhD degree at the School of VLSI Technology from Indian Institute of Engineering Science and Technology (formerly Bengal Engineering and Science University), Shibpur, Howrah, India in 2013. From 1998 to 2003, he was a senior engineer at the ASIC Product Development Centre, Texas Instruments, Bangalore, India. From 2003 to 2013, he was an assistant professor Department of Electronics and Communication Engineering, Meghnad Saha Institute of Technology, Kolkata, India. He joined the Department of Electronics and Communication Engineering, Assam Central University, Assam, India, in 2013, where he is currently a full professor. He has authored or coauthored several research papers in national and international conferences and journals. He is also the author of the book VLSI Design (New Delhi, India: Oxford Univ. Press, 2010), and co-authored the book Carbon nanotube and Graphene nanoribbon interconnect (Taylor & Francis USA: CRC. Press, 2014). His research interests include VLSI design, developing of electronic design automation tools for interconnect modeling, analyzing crosstalk and reliability, digital CMOS logic design, and modeling of nanoelectronic devices and interconnects. Corresponding author. E-mail: [email protected]

Hafizur Rahaman

Hafizur Rahaman (SM’10) received the BE degree in electrical engineering from the Bengal Engineering College, Calcutta University, Kolkata, India, in 1986, the ME degree in electrical engineering and the PhD degree in computer science and engineering, both from the Jadavpur University, Kolkata, in 1988 and 2003, respectively. From 1995 to 2003, he was a faculty member at the Indian Institute of Information Technology-Calcutta. Since 2003, he has been a faculty member of the Indian Institute of Engineering Science and Technology (formerly Bengal Engineering and Science University), Shibpur, India, where he is currently a full professor. He has contributed to VLSI computer-aided design and test, as well as to fault-tolerant computing, design and test of microfluidic biochips and emerging nanotechnologies with major publications in journals and conferences, spanning more than 15 years. He has published more than 120 research articles in archival journals and refereed conference proceedings. Dr Rahaman visited as a post-doctoral research fellow under EPSARC Grant at the Department of Computer Science, Bristol University, Bristol, UK, during 2006–2007. During 2008–2009, on the basis of his research contributions, he received the Royal Society International Fellowship Award to carry out advanced research in the Design and Verification Division of Computer Science Department, University of Bristol. He leads the VLSI design and test group at the Indian Institute of Engineering Science and Technology (formerly Bengal Engineering and Science University), Shibpur. He is the principal coordinator of the Department of Information Technology, Ministry of Communication and Information Technology; Government of India funded SMDP (special manpower development in VLSI design and related software) Research Project at Indian Institute of Engineering Science and Technology (formerly Bengal Engineering and Science University). He also received grant of Rs. 164 lacs for establishing VLSI Design Centre at Bengal Engineering and Science University. He is a member of the VLSI Society of India (VSI), the IEEE Computer Society, and ACM Sigda. He served on the conference committees of the International Conference on VLSI Design, the VLSI Design and Test Workshop (VDAT), the Asian Test Symposium (2005), and the international symposium on electronic system design (ISED) (2010-2014). E-mail: [email protected], [email protected]