Quantum-dot Cellular Automata Latches for Reversible Logic Using Wave Clocking Scheme

Abstract

The quantum-dot cellular automata computing paradigm shows particular promise in terms of density and power and also enabling a new approach to implement reversible computing. In this paper, we explore the efficient designs of various latches based on reversible logic for quantum-dot cellular automata building blocks, while applying the cell placement constraints introduced by the use of wave clock. Compared to previous literature, the proposed solutions show smaller cell count while using a potentially implementable clocking scheme for molecular QCA wave clocking. The functional correctness of the proposed latches are presented and verified using QCADesigner and HDLQ. Furthermore, we present detailed characterization and analysis, considering different cost metrics of the proposed latches. It is shown that, compared to previous literature, critical paths are decreased by 50%, 33%, 50%, 25% respectively for D-Latch, T-Latch, JK-Latch, and SR latch. There is also an improvement in timing is about 50% for D-Latch and JK-Latch, and 25% for SR-Latch.

Keywords:

• Digital circuit
• Reversible logic
• Quantum dot cellular automata (QCA)

Disclosure statement

No potential conflict of interest was reported by the author(s).

Additional information

Notes on contributors

Debajyoty Banik

Debajyoty Banik is working in the School of Computer Engineering, KIIT Bhubaneswar. He did PhD from the Department of Computer Science and Engineering, Indian Institute of Technology (IIT) Patna. He has done his Bachelor of Engineering from Bengal Engineering and Science University (IIEST), Shibpur and Master of Technology from National Institute of Technology (NIT) Durgapur. His research interest includes natural language processing (NLP), machine translation, reversible computing, quantum dot cellular automata (QCA), VLSI design and testing.

Hafizur Rahaman

Hafizur Rahaman is working as the director at School of VLSI in Indian Institute of Engineering Science and Technology Shibpur (IIEST Shibpur). He is a well-known author in the field of the VLSI design and testing, reversible computing, and fault tolerant system design. His citation count is more than 1.5K. Email: [email protected]