Fault Resistant Coplanar QCA Full Adder-Subtractor Using Clock Zone-Based Crossover

Abstract

Adders and Subtractors are an integral part of every digital information processing system. In general, it is always preferred to have a unified hardware that can perform both operations to reduce the area of circuits. The transistor technology is facing several difficulties to cope up with the targets set by Moore’s law. Researchers have started to focus on finding alternatives. Quantum-dot Cellular Automata nanotechnology is suggested by the researchers for circuit design at nanoscale levels. A full adder-subtractor circuit using clock zone and multilayer crossover are proposed in this work. The results show that they have minimal cells and area. The fault tolerance capacity of the designs to missing cell defects is also analyzed. The full adder-subtractor coplanar design is 86.7% fault resistant and the multilayer design is 76.5% fault resistant. The coherence vector simulation engine is used to perform all the simulations in QCA designer.

KEYWORDS:

• Adder
• missing cell defects
• Moore’s law
• Quantum-dot Cellular Automata (QCA)
• Subtractor

Acknowledgements

The authors thank Visvesvaraya Ph.D. Scheme (VISPHD-MEITY-1707), MeitY, Government of India for the research funding, and DST-FIST (Grant number: DST/ETI-324/2012), Government of India, for the lab facilities.

Additional information

Funding

This work was supported by MeitY; DST-FIST [grant number DST/ETI-324/2012].

Notes on contributors

R. Marshal

R Marshal received his bachelor's degree in electronics and communication engineering from Anjalai Ammal Mahalingam Engineering College, Kovilvenni in 2008. He received his master's degree in VLSI design from Kings College of Engineering, Punalkulam in 2012. He received his PhD from NIT- Tiruchirappalli, India in 2020. He is a recipient of the Visvesvaraya Scheme PhD Fellowship from MeitY, Government of India. He is also a peer reviewer in several reputed journals. His research interests include quantum-dot cellular automata, computational nanoelectronics, digital circuit design, and VLSI.

G. Lakshminarayanan

G Lakshminarayanan is currently working as a professor in the Department of ECE, NIT-Tiruchirappalli. He completed several projects funded by agencies like ISRO, DRDO, SPARC, MeitY, SMDP, UGC-UKIERI, and DST. His research interests include cognitive radio, network-on chip, VLSI based digital signal processing, and quantum-dot cellular automata. Email: [email protected]