Novel Circuit Model of Multi-walled CNT Bundle Interconnects Using Multi-valued Ternary Logic

Abstract

This research paper presents a novel circuit modeling and analysis of ternary logic for MWCNT bundle interconnects with active shielding under the influence of temperature variations. The far end crosstalk-induced noise and propagation delay of MWCNT bundle interconnects has been analyzed with and without the effect of shielding. A standard ternary inverter (STI) driver model is used to obtain the ternary logic at output. The temperature-dependent analysis is also carried out at different temperatures such as 300, 400 and 500 K. The temperature-dependent comparative analysis for MWCNT bundle, SWCNT bundle and copper interconnects with and without shielding is also performed. It has been observed that MWCNT bundle with active shielding outperforms the SWCNT and Cu by 75.7% and 84.4%, respectively. Similarly, the power dissipation is substantially reduced in the case of MWCNT bundle with respect to the Cu and SWCNT interconnects. It is also reported that the noise margin is marginally stable in ternary interconnects under the influence of temperature variation.

Keywords:

• Active shielding
• Crosstalk and propagation delay
• Cu
• Interconnects
• Multi-walled carbon nanotube (MWCNT) bundle
• Noise margin
• Temperature variation

Additional information

Notes on contributors

V. Sulochana

V Sulochana received the BTech degree in electronics and communication engineering from JNTU, Kakinada, India, in 2004, and the MTech degree from National Institute of Technology, Hamirpur, India, in 2009. She is currently pursuing the PhD degree from the UIET, PU, Chandigarh, India. Her current research interests include modeling of VLSI on-chip interconnects and TSV for 3D IC and CNT-based applications. Email: [email protected]

C. Venkataiah

C Venkataiah received the BTech degree in electronics and communication engineering from JNTUH, Hyderabad, India, in 2007, and the MTech degree from National Institute of Technology, Hamirpur, India, in 2009. He is currently pursuing the PhD degree from the JNTUK, Kakinada, India. His current research interests include modeling of VLSI on-chip interconnects and carbon-based nano interconnects. Email: [email protected]

Sunil Agrawal

Sunil Agrawal is currently a professor in UIET, PU, Chandigarh. He obtained his master’s degree in engineering from Thapar University Patiala. He obtained PhD doctorate degree from Panjab University, Chandigarh. He has many publications to his account out of which many are SCIE and scopus-indexed articles. His main areas of research include wireless communication, artificial intelligence, image processing and optical communication modeling of VLSI on-chip interconnects, and carbon-based nano interconnects. Email: [email protected]

Balwinder Singh

Balwinder Singh received the PhD degree from Guru Nanak Dev University Amritsar, India. He has more than 16 years of research and teaching experience and published several papers in reputed journals. His current research interests include VLSI testing, modeling of VLSI on-chip interconnects, and carbon-based nano interconnects.