Correlation of Core Thickness and Core Doping with Gate & Spacer Dielectric in Rectangular Core Shell Double Gate Junctionless Transistor

Abstract

The impression of gate dielectric and spacer dielectric on the performance of rectangular core shell double gate junctionless transistor (RCS-DGJLT) using extensive simulations is studied. The RCS-DGJLT brings captivating response in terms of the performance of the device. The effect of gate dielectric and spacer dielectric is studied for the first time in RCS-DGJLT. The performance of the device gets improve on increasing the dielectric constant till core thickness (t_core) = 3 nm for shell thickness (t_shell) = 4 nm. However, beyond core thickness 3 nm, the performance degrades much for high k dielectric. Further, the performance is enhanced for t_core> 3 nm and higher k dielectric on reducing the core doping. The device performance is also studied by incorporating the spacers. It has been shown that the device performance is best at t_core = 4 nm with low k gate dielectric however, the device performance degrades when high k spacer dielectric is used on the same device which is an interesting and different outcome as compared to conventional DGJLT. The ON current and ON/OFF current ratio are improved by ∼3 orders of magnitude using highly doped source/drain region(HD-S/D) with high k spacers. The results show that the core is the integral part of the device, any engineering like spacers, gate dielectrics applied to RCS-DGJLT requires the optimization of the core carefully for better device performance.

Keywords:

• Double gate
• Gate dielectric
• Junctionless
• MOSFET
• Rectangular core shell
• Spacer dielectric

ACKNOWLEDGEMENT

The authors would like to thank Cadre Design Systems for software support. We would also like to thank Electronics and Communication Engineering Department, Thapar Institute of Engineering and Technology.

Additional information

Notes on contributors

Vishal Narula

Vishal Narula is currently working towards the PhD degree at Thapar Institute of Engineering and Technology, Patiala, Punjab. He was a recipient of gold medal in MTech (Microelectronics) from Panjab University in year 2016. His main research interest includes semiconductor device simulation and modeling. The particular emphasis is on simulation, modeling of junctionless based architecture. Email: [email protected]

Amit Saini

Amit Saini is a TCAD expert at Cadre Design Systems, Ghaziabad, UP. His areas of research are nano-devices and semiconductor physics. Email: [email protected]

Mohit Agarwal

Mohit Agarwal is currently working as assistant professor in ECED with Thapar Institute of Engineering and Technology Patiala, Punjab, India. He completed his PhD from IIT Bombay. His main research interests include fabrication and characterization of semiconductor thin films, modeling and simulation of semiconductor devices design etc.