Optimization of On-Chip Meander Line Resistor by Using DOE Method

Abstract

A new analysis method for the improvement and optimization of the geometrical layout parameters associated with the on-chip n-well meander line resistor layout to have a low-quality factor (Q) and better performance operating at high frequency is investigated through factorial design experiment DOE efficient method. The factors influencing the Q-factor include the width, line length, line segment, and spacing were studied. The factorial design DOE process model was formulated using the Minitab statistical package. The result in terms of the quality factor and resistance for comparison between the proposed optimized design and conventional design layout is simulated by Sonnet electromagnetic simulation tool and validated by the theoretical mathematical prediction calculation based on an equation of lumped physical model had been presented. Results indicate that a shorter line length and line segment lead to a high impact on the improvement of the Q-factor. By the factorial design experiment, the optimized structure with a single line segment, the width of 5 µm, spacing of 1 µm, and line length of 16 µm had been established to have a lower Q-factor compared to the conventional configuration. The Q-factor was improved by 93% from 1.193 to 0.071 at the targeted 1 GHz frequency by the Sonnet EM simulation tool. The simulation result had shown comparative agreement to the theoretical mathematical predictions analysis result.

KEYWORDS:

• Factorial design experiment (DOE)
• Meander line resistor
• On-chip resistor
• Optimization
• Q-factor
• Radio frequency integrated circuits (RFICs)
• Sonnet

DISCLOSURE STATEMENT

No potential conflict of interest was reported by the author(s).

Additional information

Notes on contributors

Goon Weng Wong

Goon Weng Wong received his BEng (Hons) degree in electronic engineering from Multimedia University, Cyberjaya, Malaysia, in 2002 and his MEng degree in electronic and telecommunication from University Technology of Malaysia, Skudai, Malaysia, in 2008. He is currently pursuing his PhD degree at the Department of Electrical Engineering of University of Malaya. His research interests span topics in RF microelectronic and wireless communication. He is a Member of Institute of Engineers Malaysia (IEM) and Board of Engineers Malaysia (BEM).

Norhayati Soin

Norhayati Soin received the BEng (Hons) degree in electrical and electronic engineering from Liverpool University, UK in 1991, the MSc degree in microelectronic and IT from Liverpool John Moores University in 1999, and the PhD degree from Universiti Kebangsaan Malaysia in 2006. She is a professor in the Department of Electrical Engineering at the Faculty of Engineering, University of Malaya. Her research interests topics in microelectronics, RF micro electromechanical system (MEMS) and BIOMEMS. She is the head of VLSI research group since 2011. Email: [email protected]