Node Voltage and KCL Model-Based Low Leakage Volatile and Non-Volatile 7T SRAM Cells

Abstract

The current generation aims for Low power electronic gadgets like cell phones, PDAs, etc. This urged demand is met through adopting low power reduction techniques. These gadgets also demand the presence of cache memories, which are fabricated via Static Random Access Memory (SRAM) Cells. Now the challenge is in designing low leakage SRAM cells by adopting power reduction techniques. The proposed work of 7T based Volatile and Non-Volatile SRAM cell is carried through adopting efficient low power reduction technique referred to as Improved Self Controllable Voltage Level (I-SVL). Proposed 7T SRAM cell is based on Improved Self Controllable Voltage Level (I-SVL) technique which controls the supply voltage in Idle and Non Idle mode of SRAM cell. Also Upper-ISVL and Lower-ISVL supplies the Vdd and Vss as per the requirement there by controlling the leakage power. The proposed I-SVL based 7T Volatile and Non-Volatile is designed and simulated using Cadence Virtuoso spectre tool by using CMOS technology with gpdk 45nm. Proposed work carried is efficient in terms of sub threshold and total leakage currents in comparison with the earlier work. The obtained sub threshold and total leakage current of the proposed volatile 7T SRAM cell based on the I-SVL shows improvements in lower values with existing work by 15% and 32%. Also proposed Non-volatile based I-SVL 7T SRAM cell resulted in lesser sub threshold and total leakage current by an amount of 97% and 93% in comparison with the earlier work. The gate leakage current of proposed Non-volatile 7T SRAM cell resulted in 57% lower value in comparison with the earlier work.

KEYWORDS:

• Improved lower SVL (I-LSVL)
• Improved upper SVL (I-USVL)
• Improved – Self Controllable Voltage level (I-SVL)
• Self Controllable Voltage level (SVL)
• SRAM

Acknowledgements

This research was supported by Visvesvaraya Technological University, Belagavi, Karnataka, India. The authors thank RVCE, Bengaluru, for providing the platform to carry out the research work.

Additional information

Notes on contributors

C. S. Hemanth Kumar

C S Hemanth Kumar is working as assistant professor in the Dept of E&C, Government Engineering College, Ramangara, Bengaluru. Presently, he is a research scholar at RVCE Bengaluru, VTU, Belgaum. He has 14 years of teaching experience and published papers in international journals and conferences. His Publications are cited in Scopus, SCI and Google Scholar. His areas of interest are memory design, signal processing, VLSI design and embedded systems.

B. S. Kariyappa

B S Kariyappa is working as professor in the Dept of E&C, RVCE Bengaluru. He has 20 years of teaching experience and published more than 50 papers in international journals and conferences. His publications are cited in SCI, Scopus and Google Scholar. His areas of interest are VLSI design and embedded systems. Email: [email protected]